Simulation Results: rom_ctrl/32kb

 
17/04/2026 01:26:32 DVSim: v1.31.0 sha: ee0af46 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.68 %
  • code
  • 97.77 %
  • assert
  • 96.80 %
  • func
  • 95.47 %
  • line
  • 99.59 %
  • branch
  • 98.91 %
  • cond
  • 97.03 %
  • toggle
  • 100.00 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 4.730s 615.239us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 6.080s 183.357us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.080s 730.394us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 5.050s 173.222us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 3.860s 537.304us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.660s 244.369us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.080s 730.394us 1 1 100.00
rom_ctrl_csr_aliasing 3.860s 537.304us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 3.500s 538.338us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.870s 579.608us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 4.700s 463.099us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 14.910s 6080.819us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 9.230s 2021.592us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.390s 123.821us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 6.520s 171.708us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 6.520s 171.708us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 6.080s 183.357us 1 1 100.00
rom_ctrl_csr_rw 3.080s 730.394us 1 1 100.00
rom_ctrl_csr_aliasing 3.860s 537.304us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.820s 207.415us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 6.080s 183.357us 1 1 100.00
rom_ctrl_csr_rw 3.080s 730.394us 1 1 100.00
rom_ctrl_csr_aliasing 3.860s 537.304us 1 1 100.00
rom_ctrl_same_csr_outstanding 3.820s 207.415us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 57.520s 3194.484us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 12.540s 404.675us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 197.040s 832.844us 1 1 100.00
rom_ctrl_tl_intg_err 24.940s 815.644us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 197.040s 832.844us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 197.040s 832.844us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 57.520s 3194.484us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 57.520s 3194.484us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 57.520s 3194.484us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 57.520s 3194.484us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 57.520s 3194.484us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 197.040s 832.844us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 197.040s 832.844us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 4.730s 615.239us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 4.730s 615.239us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 4.730s 615.239us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 24.940s 815.644us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 57.520s 3194.484us 1 1 100.00
rom_ctrl_kmac_err_chk 9.230s 2021.592us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 57.520s 3194.484us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 57.520s 3194.484us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 57.520s 3194.484us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 12.540s 404.675us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 197.040s 832.844us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 166.620s 8408.520us 1 1 100.00