Simulation Results: rom_ctrl/64kb

 
17/04/2026 01:26:32 DVSim: v1.31.0 sha: ee0af46 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.05 %
  • code
  • 99.65 %
  • assert
  • 96.66 %
  • func
  • 97.85 %
  • line
  • 99.59 %
  • branch
  • 100.00 %
  • cond
  • 98.66 %
  • toggle
  • 100.00 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 6.450s 2533.516us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 11.420s 1032.198us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 6.940s 296.692us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 5.690s 1139.284us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 8.290s 300.615us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 7.160s 1020.725us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 6.940s 296.692us 1 1 100.00
rom_ctrl_csr_aliasing 8.290s 300.615us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 6.090s 699.699us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 7.470s 306.021us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 7.600s 2593.395us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 26.800s 741.831us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 14.190s 551.231us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 6.780s 1031.111us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 7.970s 699.323us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 7.970s 699.323us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 11.420s 1032.198us 1 1 100.00
rom_ctrl_csr_rw 6.940s 296.692us 1 1 100.00
rom_ctrl_csr_aliasing 8.290s 300.615us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.300s 304.480us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 11.420s 1032.198us 1 1 100.00
rom_ctrl_csr_rw 6.940s 296.692us 1 1 100.00
rom_ctrl_csr_aliasing 8.290s 300.615us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.300s 304.480us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 133.420s 4043.530us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 34.410s 1144.848us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 227.440s 1832.641us 1 1 100.00
rom_ctrl_tl_intg_err 95.520s 419.976us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 227.440s 1832.641us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 227.440s 1832.641us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 133.420s 4043.530us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 133.420s 4043.530us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 133.420s 4043.530us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 133.420s 4043.530us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 133.420s 4043.530us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 227.440s 1832.641us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 227.440s 1832.641us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 6.450s 2533.516us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 6.450s 2533.516us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 6.450s 2533.516us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 95.520s 419.976us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 133.420s 4043.530us 1 1 100.00
rom_ctrl_kmac_err_chk 14.190s 551.231us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 133.420s 4043.530us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 133.420s 4043.530us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 133.420s 4043.530us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 34.410s 1144.848us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 227.440s 1832.641us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 87.770s 3268.041us 1 1 100.00