Simulation Results: rstmgr

 
17/04/2026 01:26:32 DVSim: v1.31.0 sha: ee0af46 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.77 %
  • code
  • 99.18 %
  • assert
  • 97.86 %
  • func
  • 96.27 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.12 %
  • toggle
  • 99.25 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.440s 257.540us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.990s 129.415us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.810s 77.247us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 8.130s 2288.883us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.130s 108.402us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 0.860s 136.149us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.810s 77.247us 1 1 100.00
rstmgr_csr_aliasing 1.130s 108.402us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.970s 162.200us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.890s 356.292us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.900s 119.038us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 3.530s 922.375us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 3.530s 922.375us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 3.530s 922.375us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 3.530s 922.375us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 14.320s 5808.293us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.890s 81.333us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 3.350s 447.290us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 3.350s 447.290us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.990s 129.415us 1 1 100.00
rstmgr_csr_rw 0.810s 77.247us 1 1 100.00
rstmgr_csr_aliasing 1.130s 108.402us 1 1 100.00
rstmgr_same_csr_outstanding 1.460s 189.658us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.990s 129.415us 1 1 100.00
rstmgr_csr_rw 0.810s 77.247us 1 1 100.00
rstmgr_csr_aliasing 1.130s 108.402us 1 1 100.00
rstmgr_same_csr_outstanding 1.460s 189.658us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 20.300s 17017.711us 1 1 100.00
rstmgr_tl_intg_err 2.800s 996.210us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 20.300s 17017.711us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 20.300s 17017.711us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.800s 996.210us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.010s 151.705us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 5.970s 2251.921us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.100s 302.041us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 20.300s 17017.711us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.810s 77.247us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.810s 77.247us 1 1 100.00