Simulation Results: rv_timer

 
17/04/2026 01:26:32 DVSim: v1.31.0 sha: ee0af46 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.16 %
  • code
  • 99.38 %
  • assert
  • 96.82 %
  • func
  • 80.29 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 99.08 %
  • toggle
  • 98.45 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.860s 674.847us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.650s 73.583us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.600s 69.166us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.610s 1195.621us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.800s 38.495us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.630s 45.364us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.600s 69.166us 1 1 100.00
rv_timer_csr_aliasing 0.800s 38.495us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 1.880s 254.939us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 0.810s 822.191us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 93.170s 94900.535us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 93.170s 94900.535us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 2.910s 4899.821us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.640s 13.296us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.640s 18.890us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.590s 42.308us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.590s 42.308us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.650s 73.583us 1 1 100.00
rv_timer_csr_rw 0.600s 69.166us 1 1 100.00
rv_timer_csr_aliasing 0.800s 38.495us 1 1 100.00
rv_timer_same_csr_outstanding 0.710s 12.529us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.650s 73.583us 1 1 100.00
rv_timer_csr_rw 0.600s 69.166us 1 1 100.00
rv_timer_csr_aliasing 0.800s 38.495us 1 1 100.00
rv_timer_same_csr_outstanding 0.710s 12.529us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.860s 84.466us 1 1 100.00
rv_timer_tl_intg_err 0.800s 159.519us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 0.800s 159.519us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 1.380s 568.530us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.750s 182.265us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
rv_timer_stress_all_with_rand_reset 1.680s 306.840us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == *
rv_timer_min 49644485493398087701278211156833356857190392598587160881875514625642576066254 75
UVM_INFO @ 568529579 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 27572956878685122427164933601841658928813670910332663374001614232921138279820 75
UVM_INFO @ 254939283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*])
rv_timer_max 6462889055961210835606375659186388364607126657145855895693032997666939820382 76
UVM_INFO @ 182264963 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
rv_timer_stress_all_with_rand_reset 43048751894525664695345230160407405939849455456088831078638397496510287184897 92
UVM_INFO @ 306840028 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---