Simulation Results: spi_device/1r1w

 
17/04/2026 01:26:32 DVSim: v1.31.0 sha: ee0af46 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.05 %
  • code
  • 92.35 %
  • assert
  • 94.64 %
  • func
  • 56.15 %
  • line
  • 98.92 %
  • branch
  • 98.11 %
  • cond
  • 96.09 %
  • toggle
  • 83.54 %
  • FSM
  • 85.11 %
Validation stages
V1
100.00%
V2
92.31%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 4.070s 528.757us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.090s 50.011us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.510s 151.966us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 9.030s 822.068us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 11.700s 216.753us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.950s 164.147us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.510s 151.966us 1 1 100.00
spi_device_csr_aliasing 11.700s 216.753us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.860s 12.792us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.460s 23.948us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.710s 25.625us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.690s 8.380us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.900s 3.927us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 0.780s 38.695us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 0.780s 38.695us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 5.300s 1310.917us 1 1 100.00
spi_device_tpm_sts_read 1.040s 322.992us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 5.590s 4818.041us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 6.990s 9726.960us 1 1 100.00
spi_device_flash_all 15.050s 2241.964us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 5.790s 1999.994us 1 1 100.00
spi_device_flash_all 15.050s 2241.964us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 5.790s 1999.994us 1 1 100.00
spi_device_flash_all 15.050s 2241.964us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 15.050s 2241.964us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 2.810s 280.530us 1 1 100.00
spi_device_flash_all 15.050s 2241.964us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 2.810s 280.530us 1 1 100.00
spi_device_flash_all 15.050s 2241.964us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 2.810s 280.530us 1 1 100.00
spi_device_flash_all 15.050s 2241.964us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 2.810s 280.530us 1 1 100.00
spi_device_flash_all 15.050s 2241.964us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 2.810s 280.530us 1 1 100.00
spi_device_flash_all 15.050s 2241.964us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 22.010s 40093.078us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 1.860s 83.021us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 1.860s 83.021us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 1.860s 83.021us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 2.890s 322.243us 1 1 100.00
spi_device_read_buffer_direct 4.040s 348.081us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 1.860s 83.021us 1 1 100.00
spi_device_flash_all 15.050s 2241.964us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 15.050s 2241.964us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 15.050s 2241.964us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 12.380s 6197.278us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 12.380s 6197.278us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 4.070s 528.757us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 160.550s 82917.136us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 19.300s 3665.694us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.750s 14.657us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.700s 14.084us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 4.280s 767.273us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 4.280s 767.273us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.090s 50.011us 1 1 100.00
spi_device_csr_rw 1.510s 151.966us 1 1 100.00
spi_device_csr_aliasing 11.700s 216.753us 1 1 100.00
spi_device_same_csr_outstanding 3.770s 2599.352us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.090s 50.011us 1 1 100.00
spi_device_csr_rw 1.510s 151.966us 1 1 100.00
spi_device_csr_aliasing 11.700s 216.753us 1 1 100.00
spi_device_same_csr_outstanding 3.770s 2599.352us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 0.870s 45.408us 1 1 100.00
spi_device_tl_intg_err 6.310s 4794.134us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 6.310s 4794.134us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 42.980s 6350.221us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*])
spi_device_mem_parity 9022955974334754874043811312732461376303353231107065737768925744290483188703 76
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 4796318 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 4796318 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[912])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*])
spi_device_ram_cfg 92606341910603018088045500177414702310689020203388626151387922313394387839653 76
UVM_ERROR @ 1754866 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x7c83bd [11111001000001110111101] vs 0x0 [0])
UVM_ERROR @ 1776866 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xdbad0 [11011011101011010000] vs 0x0 [0])
UVM_ERROR @ 1863866 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xfb97bb [111110111001011110111011] vs 0x0 [0])
UVM_ERROR @ 1875866 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x9b711 [10011011011100010001] vs 0x0 [0])