Simulation Results: spi_device/2p

 
17/04/2026 01:26:32 DVSim: v1.31.0 sha: ee0af46 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.94 %
  • code
  • 92.60 %
  • assert
  • 94.62 %
  • func
  • 67.61 %
  • line
  • 98.95 %
  • branch
  • 98.21 %
  • cond
  • 95.12 %
  • toggle
  • 87.74 %
  • FSM
  • 82.98 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 142.800s 92995.141us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.150s 103.099us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 2.110s 187.227us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 8.450s 183.734us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 16.480s 1151.569us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 2.040s 343.800us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 2.110s 187.227us 1 1 100.00
spi_device_csr_aliasing 16.480s 1151.569us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.790s 28.277us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.790s 59.731us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.720s 12.305us 1 1 100.00
mem_parity 1 1 100.00
spi_device_mem_parity 1.210s 30.760us 1 1 100.00
mem_cfg 1 1 100.00
spi_device_ram_cfg 0.980s 15.683us 1 1 100.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.900s 256.350us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.900s 256.350us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 0.750s 10.313us 1 1 100.00
spi_device_tpm_sts_read 0.830s 32.623us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 5.280s 3187.766us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 2.870s 1172.932us 1 1 100.00
spi_device_flash_all 71.370s 212808.810us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 4.960s 3366.675us 1 1 100.00
spi_device_flash_all 71.370s 212808.810us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 4.960s 3366.675us 1 1 100.00
spi_device_flash_all 71.370s 212808.810us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 71.370s 212808.810us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 10.440s 2038.954us 1 1 100.00
spi_device_flash_all 71.370s 212808.810us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 10.440s 2038.954us 1 1 100.00
spi_device_flash_all 71.370s 212808.810us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 10.440s 2038.954us 1 1 100.00
spi_device_flash_all 71.370s 212808.810us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 10.440s 2038.954us 1 1 100.00
spi_device_flash_all 71.370s 212808.810us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 10.440s 2038.954us 1 1 100.00
spi_device_flash_all 71.370s 212808.810us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 24.180s 35313.126us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 1.940s 61.159us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 1.940s 61.159us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 1.940s 61.159us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 14.980s 6246.363us 1 1 100.00
spi_device_read_buffer_direct 3.000s 101.894us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 1.940s 61.159us 1 1 100.00
spi_device_flash_all 71.370s 212808.810us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 71.370s 212808.810us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 71.370s 212808.810us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 8.880s 2563.573us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 8.880s 2563.573us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 142.800s 92995.141us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 58.670s 4644.465us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 275.610s 49246.379us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.730s 57.592us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.750s 55.613us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 2.610s 753.872us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 2.610s 753.872us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.150s 103.099us 1 1 100.00
spi_device_csr_rw 2.110s 187.227us 1 1 100.00
spi_device_csr_aliasing 16.480s 1151.569us 1 1 100.00
spi_device_same_csr_outstanding 3.540s 220.332us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.150s 103.099us 1 1 100.00
spi_device_csr_rw 2.110s 187.227us 1 1 100.00
spi_device_csr_aliasing 16.480s 1151.569us 1 1 100.00
spi_device_same_csr_outstanding 3.540s 220.332us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.120s 40.706us 1 1 100.00
spi_device_tl_intg_err 17.380s 836.955us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 17.380s 836.955us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_device_flash_mode_ignore_cmds 147.910s 34239.689us 1 1 100.00