Simulation Results: spi_host

 
17/04/2026 01:26:32 DVSim: v1.31.0 sha: ee0af46 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.47 %
  • code
  • 95.03 %
  • assert
  • 94.13 %
  • func
  • 88.24 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 88.02 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 13.000s 3126.225us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 2.000s 226.963us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 47.228us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 3.000s 127.799us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 2.000s 20.707us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 1.000s 48.700us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 47.228us 1 1 100.00
spi_host_csr_aliasing 2.000s 20.707us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 15.466us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 35.077us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 2.000s 53.196us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 2.000s 159.976us 1 1 100.00
spi_host_error_cmd 2.000s 82.090us 1 1 100.00
spi_host_event 7.000s 784.219us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 1.000s 74.497us 1 1 100.00
speed 1 1 100.00
spi_host_speed 1.000s 74.497us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 1.000s 74.497us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 5.000s 200.053us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 2.000s 63.457us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 1.000s 74.497us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 1.000s 74.497us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 13.000s 3126.225us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 13.000s 3126.225us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 4.000s 342.166us 1 1 100.00
spien 1 1 100.00
spi_host_spien 11.000s 2784.348us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 41.000s 2605.616us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 2.000s 140.719us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 2.000s 159.976us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 2.000s 27.486us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 40.576us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 3.000s 192.146us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 3.000s 192.146us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 2.000s 226.963us 1 1 100.00
spi_host_csr_rw 1.000s 47.228us 1 1 100.00
spi_host_csr_aliasing 2.000s 20.707us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 51.603us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 2.000s 226.963us 1 1 100.00
spi_host_csr_rw 1.000s 47.228us 1 1 100.00
spi_host_csr_aliasing 2.000s 20.707us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 51.603us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 2.000s 56.251us 1 1 100.00
spi_host_sec_cm 1.000s 83.251us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 56.251us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_host_upper_range_clkdiv 75.000s 8488.113us 1 1 100.00