Simulation Results: sram_ctrl/main

 
17/04/2026 01:26:32 DVSim: v1.31.0 sha: ee0af46 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.41 %
  • code
  • 96.51 %
  • assert
  • 96.32 %
  • func
  • 93.40 %
  • block
  • 95.66 %
  • line
  • 95.94 %
  • branch
  • 94.01 %
  • toggle
  • 96.09 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 3.000s 349.085us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 27.420us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 2.000s 14.352us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 76.101us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 19.890us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 1535.467us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 2.000s 14.352us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 19.890us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 103.000s 6918.081us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 96.000s 20517.454us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 11.000s 2046.742us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 131.000s 16926.662us 1 1 100.00
bijection 0 1 0.00
sram_ctrl_bijection 1446.000s 2000000.000us 0 1 0.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 67.000s 54211.382us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 24.000s 11186.006us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 22.000s 24620.135us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 3.000s 1437.241us 1 1 100.00
sram_ctrl_partial_access_b2b 133.000s 26386.871us 1 1 100.00
max_throughput 1 3 33.33
sram_ctrl_max_throughput 4.000s 657.784us 0 1 0.00
sram_ctrl_throughput_w_partial_write 4.000s 2905.503us 1 1 100.00
sram_ctrl_throughput_w_readback 4.000s 2984.519us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 7.000s 1427.396us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 4.000s 6675.682us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 1931.000s 692356.397us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 65.761us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 66.432us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 2.000s 66.432us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 27.420us 1 1 100.00
sram_ctrl_csr_rw 2.000s 14.352us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 19.890us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 22.476us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 27.420us 1 1 100.00
sram_ctrl_csr_rw 2.000s 14.352us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 19.890us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 22.476us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 24.000s 17629.325us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 7.000s 2902.446us 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 1005.296us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 7.000s 2902.446us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 3.000s 1005.296us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 7.000s 1427.396us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 7.000s 1427.396us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 2.000s 14.352us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 22.000s 24620.135us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 22.000s 24620.135us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 22.000s 24620.135us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 24.000s 11186.006us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 4.000s 692.059us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 24.000s 17629.325us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 5.000s 677.245us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 349.085us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 349.085us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 22.000s 24620.135us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 7.000s 2902.446us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 24.000s 11186.006us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 7.000s 2902.446us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 7.000s 2902.446us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 3.000s 349.085us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 7.000s 2902.446us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 35.000s 6679.864us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1521) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
sram_ctrl_bijection 95959737040389275194960702182832178923470756356399600952809189928779736559171 85
UVM_INFO @ 2000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (sram_ctrl_base_vseq.sv:329) [sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-*:*], *'b0}) <= *; mask dist {'* :/ * - partial_access_pct, [* : '* - *] :/ partial_access_pct};}) Randomization failed!
sram_ctrl_max_throughput 8599175776986018802113727092469956298818600912734117850415336705519612354091 102
UVM_INFO @ 657784490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 47258157795138543756563418631937937347410607366486333221024181091756622815293 102
UVM_INFO @ 2984519000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---