Simulation Results: sram_ctrl/ret

 
17/04/2026 01:26:32 DVSim: v1.31.0 sha: ee0af46 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 90.42 %
  • code
  • 83.22 %
  • assert
  • 96.43 %
  • func
  • 91.60 %
  • block
  • 93.60 %
  • line
  • 94.37 %
  • branch
  • 89.73 %
  • toggle
  • 82.13 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
90.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 308.484us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 2.000s 33.188us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 15.271us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 149.463us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 93.140us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 65.773us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 15.271us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 93.140us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 4.000s 236.433us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 5.000s 301.062us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 2.000s 55.266us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 246.000s 15639.942us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 37.000s 3394.501us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 19.000s 2142.133us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 6.000s 3106.372us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 9.000s 1433.515us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 72.313us 1 1 100.00
sram_ctrl_partial_access_b2b 226.000s 21002.222us 1 1 100.00
max_throughput 1 3 33.33
sram_ctrl_max_throughput 1.000s 93.057us 0 1 0.00
sram_ctrl_throughput_w_partial_write 2.000s 41.391us 1 1 100.00
sram_ctrl_throughput_w_readback 1.000s 44.232us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 7.000s 163.705us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.000s 31.592us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 59.000s 6504.165us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 38.950us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 115.416us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 115.416us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 33.188us 1 1 100.00
sram_ctrl_csr_rw 1.000s 15.271us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 93.140us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 17.691us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 2.000s 33.188us 1 1 100.00
sram_ctrl_csr_rw 1.000s 15.271us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 93.140us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 17.691us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 2301.791us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 4.000s 2703.834us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 101.156us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 4.000s 2703.834us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 101.156us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 7.000s 163.705us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 7.000s 163.705us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 15.271us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 9.000s 1433.515us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 9.000s 1433.515us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 9.000s 1433.515us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 6.000s 3106.372us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 2.000s 75.478us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 3.000s 2301.791us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 1.000s 134.623us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 308.484us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 308.484us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 9.000s 1433.515us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 4.000s 2703.834us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 6.000s 3106.372us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 4.000s 2703.834us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 2703.834us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 308.484us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 2703.834us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 49.000s 10106.505us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (sram_ctrl_base_vseq.sv:329) [sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-*:*], *'b0}) <= *; mask dist {'* :/ * - partial_access_pct, [* : '* - *] :/ partial_access_pct};}) Randomization failed!
sram_ctrl_max_throughput 94194676811628970801549593168521552680874319266526129971573014877307152491409 102
UVM_INFO @ 93057230 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 110759268604390309651160187018602809963377703891160832487519568136737945716262 102
UVM_INFO @ 44231833 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---