Simulation Results: sysrst_ctrl

 
17/04/2026 01:26:32 DVSim: v1.31.0 sha: ee0af46 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 80.17 %
  • code
  • 88.11 %
  • assert
  • 86.69 %
  • func
  • 65.72 %
  • line
  • 94.49 %
  • branch
  • 95.59 %
  • cond
  • 92.12 %
  • toggle
  • 100.00 %
  • FSM
  • 58.33 %
Validation stages
V1
100.00%
V2
94.44%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 3.250s 2111.442us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 7.170s 2448.564us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 0.890s 2262.366us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 5.100s 2292.003us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 2.870s 4061.557us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 2.010s 2092.061us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 241.180s 76088.033us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 3.070s 2620.131us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 2.200s 2169.089us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 2.010s 2092.061us 1 1 100.00
sysrst_ctrl_csr_aliasing 3.070s 2620.131us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 22.890s 69222.322us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 14.270s 28859.963us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 1.510s 3208.056us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 40.190s 75196.723us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 3.200s 2529.902us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 1.860s 2188.055us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 8.590s 2843.886us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 6.390s 2611.013us 1 1 100.00
ultra_low_power_test 0 1 0.00
sysrst_ctrl_ultra_low_pwr 583.290s 2113319.797us 0 1 0.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 85.470s 42148.071us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 28.070s 14545.280us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 1.730s 2044.378us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 4.430s 2013.496us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 5.950s 2115.857us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 5.950s 2115.857us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 2.870s 4061.557us 1 1 100.00
sysrst_ctrl_csr_rw 2.010s 2092.061us 1 1 100.00
sysrst_ctrl_csr_aliasing 3.070s 2620.131us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 4.980s 7322.122us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 2.870s 4061.557us 1 1 100.00
sysrst_ctrl_csr_rw 2.010s 2092.061us 1 1 100.00
sysrst_ctrl_csr_aliasing 3.070s 2620.131us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 4.980s 7322.122us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 85.300s 42013.095us 1 1 100.00
sysrst_ctrl_tl_intg_err 43.480s 42608.748us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 43.480s 42608.748us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 6.130s 3048.990us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal_fault has unexpected timeout error
sysrst_ctrl_ultra_low_pwr 82946193640014997832685823729075371890099812193050349390688919740876254444488 658
UVM_ERROR @ 2113319796777 ps: (cip_base_scoreboard.sv:267) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_fault triggered unexpectedly
UVM_INFO @ 2113319796777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---