Simulation Results: uart

 
17/04/2026 01:26:32 DVSim: v1.31.0 sha: ee0af46 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.27 %
  • code
  • 95.21 %
  • assert
  • 97.12 %
  • func
  • 51.48 %
  • line
  • 98.86 %
  • branch
  • 96.50 %
  • cond
  • 93.93 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 0.920s 131.479us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.660s 28.394us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.760s 31.372us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.890s 60.360us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.740s 78.727us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.930s 13.955us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.760s 31.372us 1 1 100.00
uart_csr_aliasing 0.740s 78.727us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 44.960s 72418.855us 1 1 100.00
parity 2 2 100.00
uart_smoke 0.920s 131.479us 1 1 100.00
uart_tx_rx 44.960s 72418.855us 1 1 100.00
parity_error 2 2 100.00
uart_intr 34.200s 31900.855us 1 1 100.00
uart_rx_parity_err 22.120s 21291.520us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 44.960s 72418.855us 1 1 100.00
uart_intr 34.200s 31900.855us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 22.380s 41383.125us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 33.900s 51564.522us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 21.990s 32481.211us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 34.200s 31900.855us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 34.200s 31900.855us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 34.200s 31900.855us 1 1 100.00
perf 1 1 100.00
uart_perf 946.010s 33061.437us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 9.910s 14340.503us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 9.910s 14340.503us 1 1 100.00
rx_noise_filter 1 1 100.00
uart_noise_filter 17.110s 59183.191us 1 1 100.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 0.980s 676.586us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 2.280s 651.243us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 8.820s 6646.343us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 148.200s 129146.331us 1 1 100.00
stress_all 0 1 0.00
uart_stress_all 72.650s 64095.088us 0 1 0.00
alert_test 1 1 100.00
uart_alert_test 0.640s 19.139us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.810s 17.883us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.790s 629.284us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.790s 629.284us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.660s 28.394us 1 1 100.00
uart_csr_rw 0.760s 31.372us 1 1 100.00
uart_csr_aliasing 0.740s 78.727us 1 1 100.00
uart_same_csr_outstanding 0.910s 111.985us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.660s 28.394us 1 1 100.00
uart_csr_rw 0.760s 31.372us 1 1 100.00
uart_csr_aliasing 0.740s 78.727us 1 1 100.00
uart_same_csr_outstanding 0.910s 111.985us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.980s 271.527us 1 1 100.00
uart_tl_intg_err 1.470s 117.827us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.470s 117.827us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 15.380s 13399.009us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:501) scoreboard [scoreboard] rxlvl mismatch exp: * (+/-1), act: *, clk_pulses: *
uart_stress_all 21388929509239450842293049772403988283913471714131765791822149538613995066387 83
UVM_ERROR @ 63556239882 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 63556249983 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata
UVM_ERROR @ 63556260084 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty
UVM_ERROR @ 63556270185 ps: (uart_scoreboard.sv:531) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (0 [0x0] vs 255 [0xff]) reg name: uart_reg_block.rdata