Simulation Results: adc_ctrl

 
20/04/2026 17:21:27 DVSim: v1.32.0 sha: 8666f0e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 65.40 %
  • code
  • 92.09 %
  • assert
  • 91.09 %
  • func
  • 13.02 %
  • line
  • 97.97 %
  • branch
  • 96.35 %
  • cond
  • 85.77 %
  • toggle
  • 99.29 %
  • FSM
  • 81.08 %
Validation stages
V1
100.00%
V2
52.63%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 2.400s 5859.719us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 1.790s 1417.493us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 1.520s 557.030us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 23.670s 52912.874us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 1.550s 856.451us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 0.930s 539.662us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 1.520s 557.030us 1 1 100.00
adc_ctrl_csr_aliasing 1.550s 856.451us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 0 1 0.00
adc_ctrl_filters_polled 0.830s 280.418us 0 1 0.00
filters_polled_fixed 0 1 0.00
adc_ctrl_filters_polled_fixed 0.960s 463.883us 0 1 0.00
filters_interrupt 0 1 0.00
adc_ctrl_filters_interrupt 0.930s 469.661us 0 1 0.00
filters_interrupt_fixed 0 1 0.00
adc_ctrl_filters_interrupt_fixed 1.280s 410.929us 0 1 0.00
filters_wakeup 0 1 0.00
adc_ctrl_filters_wakeup 0.780s 529.040us 0 1 0.00
filters_wakeup_fixed 0 1 0.00
adc_ctrl_filters_wakeup_fixed 0.900s 340.541us 0 1 0.00
filters_both 0 1 0.00
adc_ctrl_filters_both 0.820s 393.462us 0 1 0.00
clock_gating 0 1 0.00
adc_ctrl_clock_gating 1.500s 513.080us 0 1 0.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 9.990s 4887.665us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 65.010s 40181.863us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 59.260s 102870.178us 1 1 100.00
stress_all 0 1 0.00
adc_ctrl_stress_all 1.040s 768.482us 0 1 0.00
alert_test 1 1 100.00
adc_ctrl_alert_test 0.710s 474.387us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 1.080s 488.996us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 2.010s 435.171us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 2.010s 435.171us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.790s 1417.493us 1 1 100.00
adc_ctrl_csr_rw 1.520s 557.030us 1 1 100.00
adc_ctrl_csr_aliasing 1.550s 856.451us 1 1 100.00
adc_ctrl_same_csr_outstanding 3.470s 4671.536us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.790s 1417.493us 1 1 100.00
adc_ctrl_csr_rw 1.520s 557.030us 1 1 100.00
adc_ctrl_csr_aliasing 1.550s 856.451us 1 1 100.00
adc_ctrl_same_csr_outstanding 3.470s 4671.536us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 7.610s 3951.005us 1 1 100.00
adc_ctrl_tl_intg_err 7.680s 4293.690us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 7.680s 4293.690us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
adc_ctrl_stress_all_with_rand_reset 3.510s 1818.880us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [*, *]
adc_ctrl_filters_polled 90942404118853621044678611778325302336523741551530551164621423721485610881693 389
UVM_INFO @ 280417619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 95065094128710540352244324201906023863480168782841740713825194341463138087702 389
UVM_INFO @ 463883113 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 31654746429377480763709472595373834751383902858700729414307596710992890596965 389
UVM_INFO @ 469661475 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 30931778454617366857855899796532290183373995349560660597995928798295251189969 389
UVM_INFO @ 410928941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 16461508880642706833668587033445420416410072546293564735452479402878099492508 389
UVM_INFO @ 529039837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 40762793022209796904563895367205147981293782130589036655692723532883251544306 389
UVM_INFO @ 340540677 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 18663168845579001987529973190151809442223355854416535848304732138253451422390 389
UVM_INFO @ 513080120 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 5166489146280674213035115999536296060430527632177477832244213609992940490296 389
UVM_INFO @ 393461554 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 29827061074477877917897258042598510659104245556848142732723890624482870840060 416
UVM_INFO @ 1818879612 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 73195212763779403003216034510529989676350263271536083914521528989390436294421 390
UVM_INFO @ 768481557 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---