Simulation Results: alert_handler

 
20/04/2026 17:21:27 DVSim: v1.32.0 sha: 8666f0e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.07 %
  • code
  • 93.10 %
  • assert
  • 98.42 %
  • func
  • 78.69 %
  • line
  • 99.77 %
  • branch
  • 97.92 %
  • cond
  • 91.07 %
  • toggle
  • 94.48 %
  • FSM
  • 82.26 %
Validation stages
V1
100.00%
V2
94.74%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 12.960s 718.987us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 3.980s 142.586us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 3.930s 95.419us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 118.890s 5828.607us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 45.960s 2145.754us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 5.070s 388.659us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 3.930s 95.419us 1 1 100.00
alert_handler_csr_aliasing 45.960s 2145.754us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 30.340s 1982.773us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 17.320s 1375.861us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 1769.950s 44532.251us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 24.660s 605.290us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 12.960s 718.987us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 24.380s 2535.355us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 13.440s 1252.771us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 86.280s 13628.706us 0 1 0.00
lpg 2 2 100.00
alert_handler_lpg 1313.960s 34527.982us 1 1 100.00
alert_handler_lpg_stub_clk 1666.010s 130632.437us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 870.760s 25209.001us 1 1 100.00
alert_handler_entropy_stress_test 1 1 100.00
alert_handler_entropy_stress 5.680s 303.134us 1 1 100.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 2.010s 20.912us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.420s 16.297us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 6.300s 167.391us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 6.300s 167.391us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 3.980s 142.586us 1 1 100.00
alert_handler_csr_rw 3.930s 95.419us 1 1 100.00
alert_handler_csr_aliasing 45.960s 2145.754us 1 1 100.00
alert_handler_same_csr_outstanding 22.790s 525.758us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 3.980s 142.586us 1 1 100.00
alert_handler_csr_rw 3.930s 95.419us 1 1 100.00
alert_handler_csr_aliasing 45.960s 2145.754us 1 1 100.00
alert_handler_same_csr_outstanding 22.790s 525.758us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 60.420s 3008.571us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 60.420s 3008.571us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 60.420s 3008.571us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 60.420s 3008.571us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 188.350s 2277.101us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 7.060s 178.153us 1 1 100.00
alert_handler_tl_intg_err 14.600s 626.339us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 14.600s 626.339us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 60.420s 3008.571us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 12.960s 718.987us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 12.960s 718.987us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 12.960s 718.987us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 12.960s 718.987us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 24.660s 605.290us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 1313.960s 34527.982us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 24.660s 605.290us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1769.950s 44532.251us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1769.950s 44532.251us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 7.060s 178.153us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 7.060s 178.153us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 7.060s 178.153us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 7.060s 178.153us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 7.060s 178.153us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 7.060s 178.153us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 7.060s 178.153us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 7.060s 178.153us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 7.060s 178.153us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
alert_handler_stress_all_with_rand_reset 216.160s 14031.704us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state
alert_handler_ping_timeout 48054213448713551421826872070422317099364627184233833716609619227088190366473 99
UVM_INFO @ 13628706243 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---