Simulation Results: chip

 
20/04/2026 17:21:27 DVSim: v1.32.0 sha: 8666f0e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 76.32 %
  • code
  • 84.58 %
  • assert
  • 97.37 %
  • func
  • 47.01 %
  • line
  • 93.91 %
  • branch
  • 92.32 %
  • cond
  • 88.32 %
  • toggle
  • 91.20 %
  • FSM
  • 57.14 %
Validation stages
V1
100.00%
V2
78.42%
V2S
50.00%
V3
69.23%
unmapped
70.00%
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_example_tests 4 4 100.00
chip_sw_example_flash 107.430s 2462.307us 1 1 100.00
chip_sw_example_rom 91.000s 2739.728us 1 1 100.00
chip_sw_example_manufacturer 132.360s 2513.503us 1 1 100.00
chip_sw_example_concurrency 181.020s 3506.106us 1 1 100.00
csr_hw_reset 1 1 100.00
chip_csr_hw_reset 188.930s 4523.914us 1 1 100.00
csr_rw 1 1 100.00
chip_csr_rw 280.530s 4495.347us 1 1 100.00
csr_bit_bash 1 1 100.00
chip_csr_bit_bash 3043.150s 42169.445us 1 1 100.00
csr_aliasing 1 1 100.00
chip_csr_aliasing 4147.110s 37678.379us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
chip_csr_mem_rw_with_rand_reset 562.730s 8821.368us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
chip_csr_aliasing 4147.110s 37678.379us 1 1 100.00
chip_csr_rw 280.530s 4495.347us 1 1 100.00
xbar_smoke 1 1 100.00
xbar_smoke 4.710s 47.940us 1 1 100.00
chip_sw_gpio_out 1 1 100.00
chip_sw_gpio 304.800s 4354.562us 1 1 100.00
chip_sw_gpio_in 1 1 100.00
chip_sw_gpio 304.800s 4354.562us 1 1 100.00
chip_sw_gpio_irq 1 1 100.00
chip_sw_gpio 304.800s 4354.562us 1 1 100.00
chip_sw_uart_tx_rx 1 1 100.00
chip_sw_uart_tx_rx 410.860s 4570.311us 1 1 100.00
chip_sw_uart_rx_overflow 4 4 100.00
chip_sw_uart_tx_rx 410.860s 4570.311us 1 1 100.00
chip_sw_uart_tx_rx_idx1 339.140s 3505.225us 1 1 100.00
chip_sw_uart_tx_rx_idx2 372.600s 4732.808us 1 1 100.00
chip_sw_uart_tx_rx_idx3 378.880s 3923.048us 1 1 100.00
chip_sw_uart_baud_rate 1 1 100.00
chip_sw_uart_rand_baudrate 319.350s 3765.910us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq 2 2 100.00
chip_sw_uart_tx_rx_alt_clk_freq 400.100s 4221.327us 1 1 100.00
chip_sw_uart_tx_rx_alt_clk_freq_low_speed 642.620s 8866.925us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_pin_mux 1 1 100.00
chip_padctrl_attributes 245.220s 5387.251us 1 1 100.00
chip_padctrl_attributes 1 1 100.00
chip_padctrl_attributes 245.220s 5387.251us 1 1 100.00
chip_sw_sleep_pin_mio_dio_val 0 1 0.00
chip_sw_sleep_pin_mio_dio_val 199.100s 3569.573us 0 1 0.00
chip_sw_sleep_pin_wake 1 1 100.00
chip_sw_sleep_pin_wake 166.200s 3752.789us 1 1 100.00
chip_sw_sleep_pin_retention 1 1 100.00
chip_sw_sleep_pin_retention 203.960s 4013.419us 1 1 100.00
chip_sw_tap_strap_sampling 4 4 100.00
chip_tap_straps_dev 503.670s 9107.392us 1 1 100.00
chip_tap_straps_testunlock0 265.870s 5048.531us 1 1 100.00
chip_tap_straps_rma 303.280s 5060.233us 1 1 100.00
chip_tap_straps_prod 113.180s 3019.491us 1 1 100.00
chip_sw_pattgen_ios 1 1 100.00
chip_sw_pattgen_ios 164.390s 3075.209us 1 1 100.00
chip_sw_sleep_pwm_pulses 1 1 100.00
chip_sw_sleep_pwm_pulses 849.810s 10699.716us 1 1 100.00
chip_sw_data_integrity 1 1 100.00
chip_sw_data_integrity_escalation 438.790s 5585.900us 1 1 100.00
chip_sw_instruction_integrity 1 1 100.00
chip_sw_data_integrity_escalation 438.790s 5585.900us 1 1 100.00
chip_sw_ast_clk_outputs 1 1 100.00
chip_sw_ast_clk_outputs 570.680s 7943.857us 1 1 100.00
chip_sw_ast_clk_rst_inputs 0 1 0.00
chip_sw_ast_clk_rst_inputs 1871.570s 14677.394us 0 1 0.00
chip_sw_ast_sys_clk_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 384.620s 4336.352us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 558.520s 5770.312us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3688.520s 18315.756us 1 1 100.00
chip_sw_aes_enc_jitter_en 162.730s 3084.587us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 532.390s 6189.929us 1 1 100.00
chip_sw_hmac_enc_jitter_en 221.050s 3089.184us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 667.890s 6553.803us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 158.850s 3071.731us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 398.800s 4983.794us 1 1 100.00
chip_sw_clkmgr_jitter 176.580s 2779.656us 1 1 100.00
chip_sw_ast_usb_clk_calib 1 1 100.00
chip_sw_usb_ast_clk_calib 227.360s 3163.826us 1 1 100.00
chip_sw_sensor_ctrl_ast_alerts 2 2 100.00
chip_sw_sensor_ctrl_alert 396.820s 5473.214us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 296.710s 6021.295us 1 1 100.00
chip_sw_sensor_ctrl_ast_status 1 1 100.00
chip_sw_sensor_ctrl_status 204.350s 3112.446us 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 1 1 100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup 296.710s 6021.295us 1 1 100.00
chip_sw_smoketest 17 17 100.00
chip_sw_flash_scrambling_smoketest 198.290s 3301.472us 1 1 100.00
chip_sw_aes_smoketest 191.690s 2982.581us 1 1 100.00
chip_sw_aon_timer_smoketest 148.390s 3597.159us 1 1 100.00
chip_sw_clkmgr_smoketest 165.920s 2797.597us 1 1 100.00
chip_sw_csrng_smoketest 144.080s 3126.914us 1 1 100.00
chip_sw_entropy_src_smoketest 867.490s 7126.339us 1 1 100.00
chip_sw_gpio_smoketest 162.070s 2382.488us 1 1 100.00
chip_sw_hmac_smoketest 247.080s 3860.151us 1 1 100.00
chip_sw_kmac_smoketest 221.570s 2805.946us 1 1 100.00
chip_sw_otbn_smoketest 815.950s 6618.430us 1 1 100.00
chip_sw_pwrmgr_smoketest 336.760s 6604.219us 1 1 100.00
chip_sw_pwrmgr_usbdev_smoketest 218.600s 5909.730us 1 1 100.00
chip_sw_rv_plic_smoketest 157.840s 3561.153us 1 1 100.00
chip_sw_rv_timer_smoketest 133.360s 2763.875us 1 1 100.00
chip_sw_rstmgr_smoketest 162.600s 2271.706us 1 1 100.00
chip_sw_sram_ctrl_smoketest 158.620s 3022.420us 1 1 100.00
chip_sw_uart_smoketest 180.670s 3350.933us 1 1 100.00
chip_sw_otp_smoketest 1 1 100.00
chip_sw_otp_ctrl_smoketest 159.670s 2387.244us 1 1 100.00
chip_sw_rom_functests 0 1 0.00
rom_keymgr_functest 351.360s 4777.622us 0 1 0.00
chip_sw_boot 1 1 100.00
chip_sw_uart_tx_rx_bootstrap 7846.480s 62877.872us 1 1 100.00
chip_sw_secure_boot 1 1 100.00
rom_e2e_smoke 3047.610s 14596.259us 1 1 100.00
chip_sw_rom_raw_unlock 0 1 0.00
rom_raw_unlock 167.027s 0.000us 0 1 0.00
chip_sw_power_idle_load 0 1 0.00
chip_sw_power_idle_load 245.490s 3518.157us 0 1 0.00
chip_sw_power_sleep_load 0 1 0.00
chip_sw_power_sleep_load 158.410s 3900.714us 0 1 0.00
chip_sw_exit_test_unlocked_bootstrap 1 1 100.00
chip_sw_exit_test_unlocked_bootstrap 7670.310s 54280.715us 1 1 100.00
chip_sw_inject_scramble_seed 1 1 100.00
chip_sw_inject_scramble_seed 7906.740s 58530.568us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
chip_tl_errors 49.880s 2381.496us 0 1 0.00
tl_d_illegal_access 0 1 0.00
chip_tl_errors 49.880s 2381.496us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
chip_csr_aliasing 4147.110s 37678.379us 1 1 100.00
chip_same_csr_outstanding 2660.990s 28495.907us 1 1 100.00
chip_csr_hw_reset 188.930s 4523.914us 1 1 100.00
chip_csr_rw 280.530s 4495.347us 1 1 100.00
tl_d_partial_access 4 4 100.00
chip_csr_aliasing 4147.110s 37678.379us 1 1 100.00
chip_same_csr_outstanding 2660.990s 28495.907us 1 1 100.00
chip_csr_hw_reset 188.930s 4523.914us 1 1 100.00
chip_csr_rw 280.530s 4495.347us 1 1 100.00
xbar_base_random_sequence 1 1 100.00
xbar_random 59.090s 2625.832us 1 1 100.00
xbar_random_delay 6 6 100.00
xbar_smoke_zero_delays 4.750s 45.700us 1 1 100.00
xbar_smoke_large_delays 32.420s 5058.372us 1 1 100.00
xbar_smoke_slow_rsp 54.660s 5186.614us 1 1 100.00
xbar_random_zero_delays 16.810s 243.196us 1 1 100.00
xbar_random_large_delays 281.380s 49753.667us 1 1 100.00
xbar_random_slow_rsp 90.100s 10560.149us 1 1 100.00
xbar_unmapped_address 2 2 100.00
xbar_unmapped_addr 20.590s 221.889us 1 1 100.00
xbar_error_and_unmapped_addr 10.110s 320.048us 1 1 100.00
xbar_error_cases 2 2 100.00
xbar_error_random 18.010s 803.592us 1 1 100.00
xbar_error_and_unmapped_addr 10.110s 320.048us 1 1 100.00
xbar_all_access_same_device 2 2 100.00
xbar_access_same_device 57.780s 2483.234us 1 1 100.00
xbar_access_same_device_slow_rsp 187.830s 21533.559us 1 1 100.00
xbar_all_hosts_use_same_source_id 1 1 100.00
xbar_same_source 9.380s 150.277us 1 1 100.00
xbar_stress_all 2 2 100.00
xbar_stress_all 274.230s 4600.967us 1 1 100.00
xbar_stress_all_with_error 105.420s 4061.787us 1 1 100.00
xbar_stress_with_reset 2 2 100.00
xbar_stress_all_with_rand_reset 266.410s 2624.696us 1 1 100.00
xbar_stress_all_with_reset_error 50.310s 203.341us 1 1 100.00
rom_e2e_smoke 1 1 100.00
rom_e2e_smoke 3047.610s 14596.259us 1 1 100.00
rom_e2e_shutdown_output 1 1 100.00
rom_e2e_shutdown_output 3051.590s 31817.645us 1 1 100.00
rom_e2e_shutdown_exception_c 1 1 100.00
rom_e2e_shutdown_exception_c 2946.800s 14807.353us 1 1 100.00
rom_e2e_boot_policy_valid 0 15 0.00
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 49.663s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_dev 8.157s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod 67.896s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 64.233s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_good_rma 12.980s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 168.285s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_dev 81.385s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod 73.155s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 59.564s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_good_b_bad_rma 120.319s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 138.089s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_dev 112.780s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod 93.950s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 83.067s 0.000us 0 1 0.00
rom_e2e_boot_policy_valid_a_bad_b_good_rma 90.873s 0.000us 0 1 0.00
rom_e2e_sigverify_always 0 15 0.00
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 17.860s 10.100us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_dev 20.930s 10.320us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod 17.940s 10.380us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 19.090s 10.240us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_bad_rma 17.430s 10.200us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 17.060s 10.340us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_dev 18.570s 10.120us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod 17.150s 10.220us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 21.660s 10.100us 0 1 0.00
rom_e2e_sigverify_always_a_bad_b_nothing_rma 17.690s 10.360us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 16.060s 10.300us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_dev 20.090s 10.180us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod 17.300s 10.380us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 16.670s 10.200us 0 1 0.00
rom_e2e_sigverify_always_a_nothing_b_bad_rma 17.490s 10.140us 0 1 0.00
rom_e2e_asm_init 0 5 0.00
rom_e2e_asm_init_test_unlocked0 138.508s 0.000us 0 1 0.00
rom_e2e_asm_init_dev 123.320s 0.000us 0 1 0.00
rom_e2e_asm_init_prod 8.090s 0.000us 0 1 0.00
rom_e2e_asm_init_prod_end 90.831s 0.000us 0 1 0.00
rom_e2e_asm_init_rma 83.490s 0.000us 0 1 0.00
rom_e2e_keymgr_init 3 3 100.00
rom_e2e_keymgr_init_rom_ext_meas 5890.030s 31122.729us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_no_meas 6009.480s 34991.806us 1 1 100.00
rom_e2e_keymgr_init_rom_ext_invalid_meas 5861.500s 28933.692us 1 1 100.00
rom_e2e_static_critical 1 1 100.00
rom_e2e_static_critical 3188.150s 16445.490us 1 1 100.00
chip_sw_adc_ctrl_debug_cable_irq 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2755.720s 35319.021us 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 0 1 0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2755.720s 35319.021us 0 1 0.00
chip_sw_aes_enc 2 2 100.00
chip_sw_aes_enc 131.950s 2571.800us 1 1 100.00
chip_sw_aes_enc_jitter_en 162.730s 3084.587us 1 1 100.00
chip_sw_aes_entropy 1 1 100.00
chip_sw_aes_entropy 161.970s 3112.690us 1 1 100.00
chip_sw_aes_idle 1 1 100.00
chip_sw_aes_idle 194.440s 3151.716us 1 1 100.00
chip_sw_aes_sideload 1 1 100.00
chip_sw_keymgr_sideload_aes 1130.170s 8820.693us 1 1 100.00
chip_sw_alert_handler_alerts 0 1 0.00
chip_sw_alert_test 152.940s 2850.463us 0 1 0.00
chip_sw_alert_handler_escalations 1 1 100.00
chip_sw_alert_handler_escalation 449.010s 6518.896us 1 1 100.00
chip_sw_all_escalation_resets 1 1 100.00
chip_sw_all_escalation_resets 421.480s 5537.376us 1 1 100.00
chip_sw_alert_handler_irqs 3 3 100.00
chip_plic_all_irqs_0 527.690s 5122.196us 1 1 100.00
chip_plic_all_irqs_10 312.580s 3297.549us 1 1 100.00
chip_plic_all_irqs_20 450.390s 4664.929us 1 1 100.00
chip_sw_alert_handler_entropy 1 1 100.00
chip_sw_alert_handler_entropy 166.220s 2967.144us 1 1 100.00
chip_sw_alert_handler_crashdump 1 1 100.00
chip_sw_rstmgr_alert_info 1246.810s 13742.790us 1 1 100.00
chip_sw_alert_handler_ping_timeout 1 1 100.00
chip_sw_alert_handler_ping_timeout 341.790s 4611.111us 1 1 100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_alerts 154.080s 3325.403us 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0 1 0.00
chip_sw_alert_handler_lpg_sleep_mode_pings 0.000s 0.000us 0 1 0.00
chip_sw_alert_handler_lpg_clock_off 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 757.660s 6700.008us 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 991.650s 7891.563us 1 1 100.00
chip_sw_alert_handler_ping_ok 1 1 100.00
chip_sw_alert_handler_ping_ok 772.990s 7641.436us 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 1 1 100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep 7855.940s 255511.530us 1 1 100.00
chip_sw_aon_timer_wakeup_irq 1 1 100.00
chip_sw_aon_timer_irq 231.080s 4261.162us 1 1 100.00
chip_sw_aon_timer_sleep_wakeup 1 1 100.00
chip_sw_pwrmgr_smoketest 336.760s 6604.219us 1 1 100.00
chip_sw_aon_timer_wdog_bark_irq 1 1 100.00
chip_sw_aon_timer_irq 231.080s 4261.162us 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 531.100s 8673.369us 1 1 100.00
chip_sw_aon_timer_sleep_wdog_bite_reset 1 1 100.00
chip_sw_aon_timer_wdog_bite_reset 531.100s 8673.369us 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 1 1 100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause 208.170s 6620.890us 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 1 1 100.00
chip_sw_aon_timer_wdog_lc_escalate 363.930s 6042.623us 1 1 100.00
chip_sw_clkmgr_idle_trans 4 4 100.00
chip_sw_otbn_randomness 557.920s 6251.239us 1 1 100.00
chip_sw_aes_idle 194.440s 3151.716us 1 1 100.00
chip_sw_hmac_enc_idle 177.100s 3018.255us 1 1 100.00
chip_sw_kmac_idle 175.970s 3446.062us 1 1 100.00
chip_sw_clkmgr_off_trans 4 4 100.00
chip_sw_clkmgr_off_aes_trans 263.110s 5537.227us 1 1 100.00
chip_sw_clkmgr_off_hmac_trans 268.330s 5617.214us 1 1 100.00
chip_sw_clkmgr_off_kmac_trans 246.980s 4582.807us 1 1 100.00
chip_sw_clkmgr_off_otbn_trans 310.620s 4122.719us 1 1 100.00
chip_sw_clkmgr_off_peri 1 1 100.00
chip_sw_clkmgr_off_peri 968.320s 11517.941us 1 1 100.00
chip_sw_clkmgr_div 7 7 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 400.660s 4386.020us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 416.740s 4865.317us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 345.640s 3694.347us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 346.770s 4503.485us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 421.380s 4770.427us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 402.630s 4648.127us 1 1 100.00
chip_sw_ast_clk_outputs 570.680s 7943.857us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 381.830s 6830.178us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw 2 2 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 345.640s 3694.347us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 346.770s 4503.485us 1 1 100.00
chip_sw_clkmgr_jitter 10 10 100.00
chip_sw_flash_ctrl_ops_jitter_en 384.620s 4336.352us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 558.520s 5770.312us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3688.520s 18315.756us 1 1 100.00
chip_sw_aes_enc_jitter_en 162.730s 3084.587us 1 1 100.00
chip_sw_edn_entropy_reqs_jitter 532.390s 6189.929us 1 1 100.00
chip_sw_hmac_enc_jitter_en 221.050s 3089.184us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 667.890s 6553.803us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 158.850s 3071.731us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 398.800s 4983.794us 1 1 100.00
chip_sw_clkmgr_jitter 176.580s 2779.656us 1 1 100.00
chip_sw_clkmgr_extended_range 11 11 100.00
chip_sw_clkmgr_jitter_reduced_freq 164.820s 3128.830us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en_reduced_freq 406.380s 4979.085us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en_reduced_freq 656.910s 7207.888us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq 4121.500s 25062.869us 1 1 100.00
chip_sw_aes_enc_jitter_en_reduced_freq 162.410s 3154.703us 1 1 100.00
chip_sw_hmac_enc_jitter_en_reduced_freq 172.110s 3811.319us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en_reduced_freq 968.040s 9678.392us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en_reduced_freq 191.020s 3186.422us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq 392.360s 6129.570us 1 1 100.00
chip_sw_flash_init_reduced_freq 1144.880s 24874.331us 1 1 100.00
chip_sw_csrng_edn_concurrency_reduced_freq 11875.190s 129485.370us 1 1 100.00
chip_sw_clkmgr_deep_sleep_frequency 1 1 100.00
chip_sw_ast_clk_outputs 570.680s 7943.857us 1 1 100.00
chip_sw_clkmgr_sleep_frequency 1 1 100.00
chip_sw_clkmgr_sleep_frequency 418.590s 5285.357us 1 1 100.00
chip_sw_clkmgr_reset_frequency 1 1 100.00
chip_sw_clkmgr_reset_frequency 234.400s 3504.469us 1 1 100.00
chip_sw_clkmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 421.480s 5537.376us 1 1 100.00
chip_sw_clkmgr_alert_handler_clock_enables 1 1 100.00
chip_sw_alert_handler_lpg_clkoff 757.660s 6700.008us 1 1 100.00
chip_sw_csrng_edn_cmd 1 1 100.00
chip_sw_entropy_src_csrng 825.350s 6400.679us 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read 1 1 100.00
chip_sw_csrng_fuse_en_sw_app_read_test 363.010s 5520.510us 1 1 100.00
chip_sw_csrng_lc_hw_debug_en 1 1 100.00
chip_sw_csrng_lc_hw_debug_en_test 499.250s 8050.641us 1 1 100.00
chip_sw_csrng_known_answer_tests 1 1 100.00
chip_sw_csrng_kat_test 172.450s 3230.864us 1 1 100.00
chip_sw_edn_entropy_reqs 3 3 100.00
chip_sw_csrng_edn_concurrency 5467.690s 30931.218us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 207.520s 3159.564us 1 1 100.00
chip_sw_edn_entropy_reqs 762.520s 7427.847us 1 1 100.00
chip_sw_entropy_src_ast_rng_req 1 1 100.00
chip_sw_entropy_src_ast_rng_req 207.520s 3159.564us 1 1 100.00
chip_sw_entropy_src_csrng 1 1 100.00
chip_sw_entropy_src_csrng 825.350s 6400.679us 1 1 100.00
chip_sw_entropy_src_known_answer_tests 1 1 100.00
chip_sw_entropy_src_kat_test 118.380s 2726.075us 1 1 100.00
chip_sw_flash_init 1 1 100.00
chip_sw_flash_init 1043.390s 18411.379us 1 1 100.00
chip_sw_flash_host_access 2 2 100.00
chip_sw_flash_ctrl_access 538.280s 5173.219us 1 1 100.00
chip_sw_flash_ctrl_access_jitter_en 558.520s 5770.312us 1 1 100.00
chip_sw_flash_ctrl_ops 2 2 100.00
chip_sw_flash_ctrl_ops 405.900s 4058.347us 1 1 100.00
chip_sw_flash_ctrl_ops_jitter_en 384.620s 4336.352us 1 1 100.00
chip_sw_flash_rma_unlocked 1 1 100.00
chip_sw_flash_rma_unlocked 3735.020s 44651.095us 1 1 100.00
chip_sw_flash_scramble 1 1 100.00
chip_sw_flash_init 1043.390s 18411.379us 1 1 100.00
chip_sw_flash_idle_low_power 1 1 100.00
chip_sw_flash_ctrl_idle_low_power 210.450s 4081.850us 1 1 100.00
chip_sw_flash_keymgr_seeds 1 1 100.00
chip_sw_keymgr_key_derivation 1083.680s 9202.891us 1 1 100.00
chip_sw_flash_lc_creator_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 134.720s 2366.386us 0 1 0.00
chip_sw_flash_creator_seed_wipe_on_rma 1 1 100.00
chip_sw_flash_rma_unlocked 3735.020s 44651.095us 1 1 100.00
chip_sw_flash_lc_owner_seed_sw_rw_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 134.720s 2366.386us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 134.720s 2366.386us 0 1 0.00
chip_sw_flash_lc_iso_part_sw_wr_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 134.720s 2366.386us 0 1 0.00
chip_sw_flash_lc_seed_hw_rd_en 0 1 0.00
chip_sw_flash_ctrl_lc_rw_en 134.720s 2366.386us 0 1 0.00
chip_sw_flash_lc_escalate_en 1 1 100.00
chip_sw_all_escalation_resets 421.480s 5537.376us 1 1 100.00
chip_sw_flash_prim_tl_access 1 1 100.00
chip_prim_tl_access 359.600s 10851.882us 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 1 1 100.00
chip_sw_flash_ctrl_clock_freqs 573.750s 5647.889us 1 1 100.00
chip_sw_flash_ctrl_escalation_reset 1 1 100.00
chip_sw_flash_crash_alert 349.150s 5200.349us 1 1 100.00
chip_sw_flash_ctrl_write_clear 1 1 100.00
chip_sw_flash_crash_alert 349.150s 5200.349us 1 1 100.00
chip_sw_hmac_enc 2 2 100.00
chip_sw_hmac_enc 170.890s 3466.872us 1 1 100.00
chip_sw_hmac_enc_jitter_en 221.050s 3089.184us 1 1 100.00
chip_sw_hmac_idle 1 1 100.00
chip_sw_hmac_enc_idle 177.100s 3018.255us 1 1 100.00
chip_sw_hmac_all_configurations 1 1 100.00
chip_sw_hmac_oneshot 1719.160s 11476.745us 1 1 100.00
chip_sw_hmac_multistream_mode 1 1 100.00
chip_sw_hmac_multistream 733.880s 6107.661us 1 1 100.00
chip_sw_i2c_host_tx_rx 3 3 100.00
chip_sw_i2c_host_tx_rx 367.910s 5114.791us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx1 422.320s 5057.469us 1 1 100.00
chip_sw_i2c_host_tx_rx_idx2 407.480s 5221.785us 1 1 100.00
chip_sw_i2c_device_tx_rx 1 1 100.00
chip_sw_i2c_device_tx_rx 354.500s 4406.419us 1 1 100.00
chip_sw_keymgr_key_derivation 2 2 100.00
chip_sw_keymgr_key_derivation 1083.680s 9202.891us 1 1 100.00
chip_sw_keymgr_key_derivation_jitter_en 667.890s 6553.803us 1 1 100.00
chip_sw_keymgr_sideload_kmac 1 1 100.00
chip_sw_keymgr_sideload_kmac 875.170s 8833.823us 1 1 100.00
chip_sw_keymgr_sideload_aes 1 1 100.00
chip_sw_keymgr_sideload_aes 1130.170s 8820.693us 1 1 100.00
chip_sw_keymgr_sideload_otbn 1 1 100.00
chip_sw_keymgr_sideload_otbn 2300.020s 11671.306us 1 1 100.00
chip_sw_kmac_enc 3 3 100.00
chip_sw_kmac_mode_cshake 190.550s 2970.442us 1 1 100.00
chip_sw_kmac_mode_kmac 168.700s 3214.966us 1 1 100.00
chip_sw_kmac_mode_kmac_jitter_en 158.850s 3071.731us 1 1 100.00
chip_sw_kmac_app_keymgr 1 1 100.00
chip_sw_keymgr_key_derivation 1083.680s 9202.891us 1 1 100.00
chip_sw_kmac_app_lc 1 1 100.00
chip_sw_lc_ctrl_transition 605.600s 12852.765us 1 1 100.00
chip_sw_kmac_app_rom 1 1 100.00
chip_sw_kmac_app_rom 133.500s 3026.938us 1 1 100.00
chip_sw_kmac_entropy 1 1 100.00
chip_sw_kmac_entropy 595.800s 6226.996us 1 1 100.00
chip_sw_kmac_idle 1 1 100.00
chip_sw_kmac_idle 175.970s 3446.062us 1 1 100.00
chip_sw_lc_ctrl_alert_handler_escalation 1 1 100.00
chip_sw_alert_handler_escalation 449.010s 6518.896us 1 1 100.00
chip_sw_lc_ctrl_jtag_access 3 3 100.00
chip_tap_straps_dev 503.670s 9107.392us 1 1 100.00
chip_tap_straps_rma 303.280s 5060.233us 1 1 100.00
chip_tap_straps_prod 113.180s 3019.491us 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 134.360s 2872.190us 1 1 100.00
chip_sw_lc_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 605.600s 12852.765us 1 1 100.00
chip_sw_lc_ctrl_transitions 1 1 100.00
chip_sw_lc_ctrl_transition 605.600s 12852.765us 1 1 100.00
chip_sw_lc_ctrl_kmac_req 1 1 100.00
chip_sw_lc_ctrl_transition 605.600s 12852.765us 1 1 100.00
chip_sw_lc_ctrl_key_div 1 1 100.00
chip_sw_keymgr_key_derivation_prod 855.800s 7479.797us 1 1 100.00
chip_sw_lc_ctrl_broadcast 19 22 86.36
chip_sw_flash_ctrl_lc_rw_en 134.720s 2366.386us 0 1 0.00
chip_sw_flash_rma_unlocked 3735.020s 44651.095us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_test_unlocked0 217.820s 3041.183us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 674.480s 8025.135us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 555.940s 7662.050us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 510.530s 5953.175us 0 1 0.00
chip_sw_lc_ctrl_transition 605.600s 12852.765us 1 1 100.00
chip_sw_keymgr_key_derivation 1083.680s 9202.891us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 394.130s 8888.468us 1 1 100.00
chip_sw_sram_ctrl_execution_main 515.470s 9000.786us 1 1 100.00
chip_prim_tl_access 359.600s 10851.882us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_lc 381.830s 6830.178us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0 400.660s 4386.020us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0 416.740s 4865.317us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_dev 345.640s 3694.347us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_dev 346.770s 4503.485us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_fast_rma 421.380s 4770.427us 1 1 100.00
chip_sw_clkmgr_external_clk_src_for_sw_slow_rma 402.630s 4648.127us 1 1 100.00
chip_tap_straps_dev 503.670s 9107.392us 1 1 100.00
chip_tap_straps_rma 303.280s 5060.233us 1 1 100.00
chip_tap_straps_prod 113.180s 3019.491us 1 1 100.00
chip_rv_dm_lc_disabled 47.920s 1712.645us 0 1 0.00
chip_lc_scrap 4 4 100.00
chip_sw_lc_ctrl_rma_to_scrap 186.700s 4094.262us 1 1 100.00
chip_sw_lc_ctrl_raw_to_scrap 80.860s 3596.014us 1 1 100.00
chip_sw_lc_ctrl_test_locked0_to_scrap 84.430s 2868.129us 1 1 100.00
chip_sw_lc_ctrl_rand_to_scrap 162.080s 3253.002us 1 1 100.00
chip_lc_test_locked 1 2 50.00
chip_sw_lc_walkthrough_testunlocks 1754.540s 24831.922us 1 1 100.00
chip_rv_dm_lc_disabled 47.920s 1712.645us 0 1 0.00
chip_sw_lc_walkthrough 2 5 40.00
chip_sw_lc_walkthrough_dev 728.050s 12617.634us 0 1 0.00
chip_sw_lc_walkthrough_prod 610.030s 9095.128us 0 1 0.00
chip_sw_lc_walkthrough_prodend 674.050s 9764.816us 1 1 100.00
chip_sw_lc_walkthrough_rma 351.670s 6019.117us 0 1 0.00
chip_sw_lc_walkthrough_testunlocks 1754.540s 24831.922us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock 2 3 66.67
chip_sw_lc_ctrl_volatile_raw_unlock 66.810s 2953.849us 1 1 100.00
chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz 53.800s 2000.789us 1 1 100.00
rom_volatile_raw_unlock 37.283s 0.000us 0 1 0.00
chip_sw_otbn_op 2 2 100.00
chip_sw_otbn_ecdsa_op_irq 3553.720s 17599.427us 1 1 100.00
chip_sw_otbn_ecdsa_op_irq_jitter_en 3688.520s 18315.756us 1 1 100.00
chip_sw_otbn_rnd_entropy 1 1 100.00
chip_sw_otbn_randomness 557.920s 6251.239us 1 1 100.00
chip_sw_otbn_urnd_entropy 1 1 100.00
chip_sw_otbn_randomness 557.920s 6251.239us 1 1 100.00
chip_sw_otbn_idle 1 1 100.00
chip_sw_otbn_randomness 557.920s 6251.239us 1 1 100.00
chip_sw_otbn_mem_scramble 1 1 100.00
chip_sw_otbn_mem_scramble 272.720s 3725.760us 1 1 100.00
chip_otp_ctrl_init 1 1 100.00
chip_sw_lc_ctrl_transition 605.600s 12852.765us 1 1 100.00
chip_sw_otp_ctrl_keys 5 5 100.00
chip_sw_flash_init 1043.390s 18411.379us 1 1 100.00
chip_sw_otbn_mem_scramble 272.720s 3725.760us 1 1 100.00
chip_sw_keymgr_key_derivation 1083.680s 9202.891us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 310.240s 4288.632us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 141.130s 2514.459us 1 1 100.00
chip_sw_otp_ctrl_entropy 5 5 100.00
chip_sw_flash_init 1043.390s 18411.379us 1 1 100.00
chip_sw_otbn_mem_scramble 272.720s 3725.760us 1 1 100.00
chip_sw_keymgr_key_derivation 1083.680s 9202.891us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access 310.240s 4288.632us 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 141.130s 2514.459us 1 1 100.00
chip_sw_otp_ctrl_program 1 1 100.00
chip_sw_lc_ctrl_transition 605.600s 12852.765us 1 1 100.00
chip_sw_otp_ctrl_program_error 1 1 100.00
chip_sw_lc_ctrl_program_error 367.460s 5205.064us 1 1 100.00
chip_sw_otp_ctrl_hw_cfg0 1 1 100.00
chip_sw_lc_ctrl_otp_hw_cfg0 134.360s 2872.190us 1 1 100.00
chip_sw_otp_ctrl_lc_signals 5 6 83.33
chip_sw_otp_ctrl_lc_signals_test_unlocked0 217.820s 3041.183us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_dev 674.480s 8025.135us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_prod 555.940s 7662.050us 1 1 100.00
chip_sw_otp_ctrl_lc_signals_rma 510.530s 5953.175us 0 1 0.00
chip_sw_lc_ctrl_transition 605.600s 12852.765us 1 1 100.00
chip_prim_tl_access 359.600s 10851.882us 1 1 100.00
chip_sw_otp_prim_tl_access 1 1 100.00
chip_prim_tl_access 359.600s 10851.882us 1 1 100.00
chip_sw_otp_ctrl_dai_lock 1 1 100.00
chip_sw_otp_ctrl_dai_lock 804.690s 7488.945us 1 1 100.00
chip_sw_pwrmgr_external_full_reset 1 1 100.00
chip_sw_pwrmgr_full_aon_reset 246.910s 5925.372us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups 1035.950s 25699.679us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups 294.300s 8161.127us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_por_reset 0 1 0.00
chip_sw_pwrmgr_deep_sleep_por_reset 406.810s 7234.572us 0 1 0.00
chip_sw_pwrmgr_normal_sleep_por_reset 1 1 100.00
chip_sw_pwrmgr_normal_sleep_por_reset 383.420s 6929.816us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups 1226.020s 25805.756us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 1 2 50.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 208.990s 6172.754us 0 1 0.00
chip_sw_aon_timer_wdog_bite_reset 531.100s 8673.369us 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 1 1 100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs 997.100s 11069.762us 1 1 100.00
chip_sw_pwrmgr_wdog_reset 1 1 100.00
chip_sw_pwrmgr_wdog_reset 346.220s 4334.200us 1 1 100.00
chip_sw_pwrmgr_aon_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_full_aon_reset 246.910s 5925.372us 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_main_power_glitch_reset 290.330s 4841.869us 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset 2344.470s 33577.136us 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 1 1 100.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset 387.460s 7498.374us 1 1 100.00
chip_sw_pwrmgr_sleep_power_glitch_reset 0 1 0.00
chip_sw_pwrmgr_sleep_power_glitch_reset 148.320s 3223.189us 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 0 1 0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 223.910s 6125.098us 0 1 0.00
chip_sw_pwrmgr_sysrst_ctrl_reset 1 2 50.00
chip_sw_pwrmgr_sysrst_ctrl_reset 1703.540s 13181.695us 0 1 0.00
chip_sw_pwrmgr_all_reset_reqs 945.930s 10970.781us 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1 1 100.00
chip_sw_pwrmgr_b2b_sleep_reset_req 1300.330s 28855.917us 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 1 1 100.00
chip_sw_pwrmgr_sleep_disabled 199.370s 2872.162us 1 1 100.00
chip_sw_pwrmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 421.480s 5537.376us 1 1 100.00
chip_sw_rom_access 1 1 100.00
chip_sw_rom_ctrl_integrity_check 394.130s 8888.468us 1 1 100.00
chip_sw_rom_ctrl_integrity_check 1 1 100.00
chip_sw_rom_ctrl_integrity_check 394.130s 8888.468us 1 1 100.00
chip_sw_rstmgr_non_sys_reset_info 3 4 75.00
chip_sw_pwrmgr_all_reset_reqs 945.930s 10970.781us 1 1 100.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs 223.910s 6125.098us 0 1 0.00
chip_sw_pwrmgr_wdog_reset 346.220s 4334.200us 1 1 100.00
chip_sw_pwrmgr_smoketest 336.760s 6604.219us 1 1 100.00
chip_sw_rstmgr_sys_reset_info 1 1 100.00
chip_rv_dm_ndm_reset_req 273.880s 4623.644us 1 1 100.00
chip_sw_rstmgr_cpu_info 1 1 100.00
chip_sw_rstmgr_cpu_info 467.010s 6015.899us 1 1 100.00
chip_sw_rstmgr_sw_req_reset 1 1 100.00
chip_sw_rstmgr_sw_req 253.430s 4428.194us 1 1 100.00
chip_sw_rstmgr_alert_info 1 1 100.00
chip_sw_rstmgr_alert_info 1246.810s 13742.790us 1 1 100.00
chip_sw_rstmgr_sw_rst 1 1 100.00
chip_sw_rstmgr_sw_rst 157.250s 3048.100us 1 1 100.00
chip_sw_rstmgr_escalation_reset 1 1 100.00
chip_sw_all_escalation_resets 421.480s 5537.376us 1 1 100.00
chip_sw_rstmgr_alert_handler_reset_enables 1 1 100.00
chip_sw_alert_handler_lpg_reset_toggle 991.650s 7891.563us 1 1 100.00
chip_sw_nmi_irq 1 1 100.00
chip_sw_rv_core_ibex_nmi_irq 492.950s 5099.200us 1 1 100.00
chip_sw_rv_core_ibex_rnd 1 1 100.00
chip_sw_rv_core_ibex_rnd 478.560s 4942.298us 1 1 100.00
chip_sw_rv_core_ibex_address_translation 1 1 100.00
chip_sw_rv_core_ibex_address_translation 178.530s 2985.966us 1 1 100.00
chip_sw_rv_core_ibex_icache_scrambled_access 1 1 100.00
chip_sw_rv_core_ibex_icache_invalidate 141.130s 2514.459us 1 1 100.00
chip_sw_rv_core_ibex_fault_dump 1 1 100.00
chip_sw_rstmgr_cpu_info 467.010s 6015.899us 1 1 100.00
chip_sw_rv_core_ibex_double_fault 1 1 100.00
chip_sw_rstmgr_cpu_info 467.010s 6015.899us 1 1 100.00
chip_jtag_csr_rw 1 1 100.00
chip_jtag_csr_rw 173.240s 4481.968us 1 1 100.00
chip_jtag_mem_access 1 1 100.00
chip_jtag_mem_access 801.540s 13259.681us 1 1 100.00
chip_rv_dm_ndm_reset_req 1 1 100.00
chip_rv_dm_ndm_reset_req 273.880s 4623.644us 1 1 100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 0 1 0.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 204.580s 4015.455us 0 1 0.00
chip_rv_dm_access_after_wakeup 1 1 100.00
chip_sw_rv_dm_access_after_wakeup 295.530s 5895.539us 1 1 100.00
chip_sw_rv_dm_jtag_tap_sel 1 1 100.00
chip_tap_straps_rma 303.280s 5060.233us 1 1 100.00
chip_rv_dm_lc_disabled 0 1 0.00
chip_rv_dm_lc_disabled 47.920s 1712.645us 0 1 0.00
chip_sw_plic_all_irqs 3 3 100.00
chip_plic_all_irqs_0 527.690s 5122.196us 1 1 100.00
chip_plic_all_irqs_10 312.580s 3297.549us 1 1 100.00
chip_plic_all_irqs_20 450.390s 4664.929us 1 1 100.00
chip_sw_plic_sw_irq 1 1 100.00
chip_sw_plic_sw_irq 155.450s 2607.714us 1 1 100.00
chip_sw_timer 1 1 100.00
chip_sw_rv_timer_irq 178.040s 3155.785us 1 1 100.00
chip_sw_spi_device_flash_mode 1 1 100.00
rom_e2e_smoke 3047.610s 14596.259us 1 1 100.00
chip_sw_spi_device_pass_through 1 1 100.00
chip_sw_spi_device_pass_through 572.130s 8515.992us 1 1 100.00
chip_sw_spi_device_pass_through_collision 0 1 0.00
chip_sw_spi_device_pass_through_collision 173.110s 2993.199us 0 1 0.00
chip_sw_spi_device_tpm 1 1 100.00
chip_sw_spi_device_tpm 198.130s 3539.458us 1 1 100.00
chip_sw_spi_host_tx_rx 1 1 100.00
chip_sw_spi_host_tx_rx 145.790s 2560.442us 1 1 100.00
chip_sw_sram_scrambled_access 2 2 100.00
chip_sw_sram_ctrl_scrambled_access 310.240s 4288.632us 1 1 100.00
chip_sw_sram_ctrl_scrambled_access_jitter_en 398.800s 4983.794us 1 1 100.00
chip_sw_sleep_sram_ret_contents 2 2 100.00
chip_sw_sleep_sram_ret_contents_no_scramble 318.720s 8192.830us 1 1 100.00
chip_sw_sleep_sram_ret_contents_scramble 324.810s 6672.987us 1 1 100.00
chip_sw_sram_execution 1 1 100.00
chip_sw_sram_ctrl_execution_main 515.470s 9000.786us 1 1 100.00
chip_sw_sram_lc_escalation 2 2 100.00
chip_sw_all_escalation_resets 421.480s 5537.376us 1 1 100.00
chip_sw_data_integrity_escalation 438.790s 5585.900us 1 1 100.00
chip_sw_sysrst_ctrl_reset 1 2 50.00
chip_sw_pwrmgr_sysrst_ctrl_reset 1703.540s 13181.695us 0 1 0.00
chip_sw_sysrst_ctrl_reset 977.530s 24445.766us 1 1 100.00
chip_sw_sysrst_ctrl_inputs 1 1 100.00
chip_sw_sysrst_ctrl_inputs 166.820s 2889.970us 1 1 100.00
chip_sw_sysrst_ctrl_outputs 1 1 100.00
chip_sw_sysrst_ctrl_outputs 194.450s 3635.342us 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 1 1 100.00
chip_sw_sysrst_ctrl_in_irq 339.030s 4594.396us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_wakeup 1 1 100.00
chip_sw_sysrst_ctrl_reset 977.530s 24445.766us 1 1 100.00
chip_sw_sysrst_ctrl_sleep_reset 1 1 100.00
chip_sw_sysrst_ctrl_reset 977.530s 24445.766us 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2507.900s 20252.347us 1 1 100.00
chip_sw_sysrst_ctrl_flash_wp_l 1 1 100.00
chip_sw_sysrst_ctrl_ec_rst_l 2507.900s 20252.347us 1 1 100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 1 2 50.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup 282.300s 5616.390us 1 1 100.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 2755.720s 35319.021us 0 1 0.00
chip_sw_usbdev_vbus 1 1 100.00
chip_sw_usbdev_vbus 116.950s 2735.078us 1 1 100.00
chip_sw_usbdev_pullup 1 1 100.00
chip_sw_usbdev_pullup 174.930s 3469.017us 1 1 100.00
chip_sw_usbdev_aon_pullup 1 1 100.00
chip_sw_usbdev_aon_pullup 254.830s 3725.521us 1 1 100.00
chip_sw_usbdev_setup_rx 1 1 100.00
chip_sw_usbdev_setuprx 308.580s 4270.643us 1 1 100.00
chip_sw_usbdev_config_host 1 1 100.00
chip_sw_usbdev_config_host 984.640s 7997.300us 1 1 100.00
chip_sw_usbdev_pincfg 1 1 100.00
chip_sw_usbdev_pincfg 5049.370s 31946.750us 1 1 100.00
chip_sw_usbdev_tx_rx 1 1 100.00
chip_sw_usbdev_dpi 1841.710s 12398.749us 1 1 100.00
chip_sw_usbdev_toggle_restore 1 1 100.00
chip_sw_usbdev_toggle_restore 150.060s 2823.056us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_aes_masking_off 1 1 100.00
chip_sw_aes_masking_off 200.470s 3091.121us 1 1 100.00
chip_sw_rv_core_ibex_lockstep_glitch 0 1 0.00
chip_sw_rv_core_ibex_lockstep_glitch 94.520s 2580.042us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
chip_sw_coremark 1 1 100.00
chip_sw_coremark 10374.650s 71574.520us 1 1 100.00
chip_sw_power_max_load 1 1 100.00
chip_sw_power_virus 1051.000s 6986.573us 1 1 100.00
rom_e2e_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 152.150s 3365.438us 0 1 0.00
rom_e2e_jtag_debug_dev 418.080s 5553.909us 0 1 0.00
rom_e2e_jtag_debug_rma 621.290s 14816.262us 0 1 0.00
rom_e2e_jtag_inject 1 3 33.33
rom_e2e_jtag_inject_test_unlocked0 189.470s 4474.706us 1 1 100.00
rom_e2e_jtag_inject_dev 64.920s 2163.484us 0 1 0.00
rom_e2e_jtag_inject_rma 198.540s 4277.248us 0 1 0.00
rom_e2e_self_hash 0 1 0.00
rom_e2e_self_hash 46.361s 0.000us 0 1 0.00
chip_sw_clkmgr_jitter_cycle_measurements 0 1 0.00
chip_sw_clkmgr_jitter_frequency 297.300s 3867.639us 0 1 0.00
chip_sw_edn_boot_mode 1 1 100.00
chip_sw_edn_boot_mode 312.810s 2871.887us 1 1 100.00
chip_sw_edn_auto_mode 1 1 100.00
chip_sw_edn_auto_mode 890.820s 5629.593us 1 1 100.00
chip_sw_edn_sw_mode 1 1 100.00
chip_sw_edn_sw_mode 1071.810s 7758.124us 1 1 100.00
chip_sw_edn_kat 1 1 100.00
chip_sw_edn_kat 223.460s 2635.996us 1 1 100.00
chip_sw_flash_memory_protection 1 1 100.00
chip_sw_flash_ctrl_mem_protection 555.530s 5010.377us 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 1 1 100.00
chip_sw_otp_ctrl_vendor_test_csr_access 59.710s 2388.621us 1 1 100.00
chip_sw_otp_ctrl_escalation 0 1 0.00
chip_sw_otp_ctrl_escalation 200.750s 3086.941us 0 1 0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up 1 1 100.00
chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up 352.370s 6307.098us 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 1 1 100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active 368.780s 5108.058us 1 1 100.00
chip_sw_all_resets 1 1 100.00
chip_sw_pwrmgr_all_reset_reqs 945.930s 10970.781us 1 1 100.00
chip_rv_dm_perform_debug 0 3 0.00
rom_e2e_jtag_debug_test_unlocked0 152.150s 3365.438us 0 1 0.00
rom_e2e_jtag_debug_dev 418.080s 5553.909us 0 1 0.00
rom_e2e_jtag_debug_rma 621.290s 14816.262us 0 1 0.00
chip_sw_rv_dm_access_after_hw_reset 1 1 100.00
chip_sw_rv_dm_access_after_escalation_reset 385.400s 5027.938us 1 1 100.00
chip_sw_plic_alerts 1 1 100.00
chip_sw_all_escalation_resets 421.480s 5537.376us 1 1 100.00
tick_configuration 1 1 100.00
chip_sw_rv_timer_systick_test 5857.420s 37970.100us 1 1 100.00
counter_wrap 1 1 100.00
chip_sw_rv_timer_systick_test 5857.420s 37970.100us 1 1 100.00
chip_sw_spi_device_output_when_disabled_or_sleeping 1 1 100.00
chip_sw_spi_device_pinmux_sleep_retention 150.010s 3104.686us 1 1 100.00
chip_sw_uart_watermarks 1 1 100.00
chip_sw_uart_tx_rx 410.860s 4570.311us 1 1 100.00
chip_sw_usbdev_stream 1 1 100.00
chip_sw_usbdev_stream 3036.200s 18979.457us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 7 10 70.00
chip_sival_flash_info_access 175.340s 3564.179us 1 1 100.00
chip_sw_rstmgr_rst_cnsty_escalation 451.040s 6049.337us 1 1 100.00
chip_sw_otp_ctrl_rot_auth_config 4.940s 0.000us 0 1 0.00
chip_sw_otp_ctrl_ecc_error_vendor_test 138.840s 2665.878us 1 1 100.00
chip_sw_otp_ctrl_descrambling 209.480s 3342.392us 1 1 100.00
chip_sw_pwrmgr_lowpower_cancel 180.340s 3278.782us 0 1 0.00
chip_sw_pwrmgr_sleep_wake_5_bug 7.939s 0.000us 0 1 0.00
chip_sw_flash_ctrl_write_clear 174.520s 3221.389us 1 1 100.00
ate_bootstrap_flash_erase 6887.930s 45270.721us 1 1 100.00
ate_bootstrap_disjoint 10283.730s 84688.632us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [*] vs *xz [z]) for MIO[*]
chip_sw_sleep_pin_mio_dio_val 110550745334189911757907091935576624676581083733711638917516156929605368560970 451
UVM_INFO @ 3569.572500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_spi_passthrough_collision_vseq.sv:183) virtual_sequencer [chip_sw_spi_passthrough_collision_vseq] Compare mismatch
chip_sw_spi_device_pass_through_collision 106495519800226409627538216362023010575958943437815734939913243374569863598976 322
host_rsp:
-------------------------------------------------------------------------
Name Type Size Value
-------------------------------------------------------------------------
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_flash_ctrl_lc_rw_en 35298129534658096764462507543434584752133682332498518630507349583079224507257 309
UVM_INFO @ 2366.386450 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *
chip_sw_otp_ctrl_lc_signals_rma 7498718818976622739176593438689383460498566827976986517646732738995675243481 342
UVM_INFO @ 5953.175160 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
chip_sw_otp_ctrl_escalation 4916120027419740944199292811690815370453725575724499157167440897199487150807 316
UVM_ERROR @ 3086.941242 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A
UVM_INFO @ 3086.941242 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode
chip_sw_otp_ctrl_rot_auth_config 88792098119928957337991061523168412728506545474812205722627055788947749734431 282
UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_lc_walkthrough_dev 114558657861708212876004915649640577115659583501084167000772853681248787950124 369
UVM_INFO @ 12617.633744 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_prod 51801205166265498194768758252273076717057109345853783695053918339469794428357 369
UVM_INFO @ 9095.128204 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_lc_walkthrough_rma 43322734612510958277731765376830133474280804305625573731799506680310234439656 341
UVM_INFO @ 6019.117154 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_sysrst_ctrl_test_sim_dv(sw/device/tests/sim_dv/pwrmgr_sysrst_ctrl_test.c:82)] CHECK-fail: Timeout waiting for sysrst reset!
chip_sw_pwrmgr_sysrst_ctrl_reset 76024738911931653504446400509541660216827212898992821529358994180462479351468 313
UVM_INFO @ 13181.695046 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))'
chip_sw_pwrmgr_random_sleep_all_reset_reqs 66024104434780304547238277024955790658981769187604515803091235902404607599723 315
UVM_ERROR @ 6125.098000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 6125.098000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_all_reset_reqs 68772790568625052375806151111528233445808423149614725614852931721401684978609 314
UVM_ERROR @ 6172.754000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 6172.754000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
chip_sw_pwrmgr_deep_sleep_por_reset 17771278970129206649100378974239997415654778287969222181922679578528858558704 325
UVM_ERROR @ 7234.571500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
UVM_INFO @ 7234.571500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))'
chip_sw_pwrmgr_sleep_power_glitch_reset 65776283667724909115215866998098390664059944099934817454442601936068478768376 313
UVM_ERROR @ 3223.189216 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A
UVM_INFO @ 3223.189216 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns
chip_sw_adc_ctrl_sleep_debug_cable_wakeup 99060328319058897146010239473483726642965401509931992889372926086379718692408 332
UVM_INFO @ 35319.020809 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:367)] CHECK-fail: Expect alert *!
chip_sw_alert_test 114235900257493178628398578713582578203929010802018740225587016784442248133728 307
UVM_INFO @ 2850.462910 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
chip_sw_alert_handler_lpg_sleep_mode_alerts 93916471391874188311628637410282941264289330999247171156977413028286692804284 308
UVM_INFO @ 3325.402872 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job killed!
chip_sw_alert_handler_lpg_sleep_mode_pings 89026673962915581391610647959638536876637958023474227304470261271065695686598 None
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted *, but saw *).
chip_tl_errors 115733841653311727753639011538608589599367795058362988017171537255198402128510 217
TL item was: req: (cip_tl_seq_item@32391) { a_addr: 'h1064c a_data: 'h6f6f4791 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1b a_opcode: 'h4 a_user: 'h1ae12 d_param: 'h0 d_source: 'h1b d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 }
Reasons for predicted error: '{"Fetch from CSR"} .
UVM_INFO @ 2381.496056 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
chip_sw_clkmgr_jitter_frequency 65403829587389164236142748524563467791034496397986996023878956943540287665452 343
UVM_INFO @ 3867.639342 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for !get_wakeup_status()
chip_sw_pwrmgr_lowpower_cancel 106305012544236956975759060784260509059526566559341638863341013194769823023007 311
UVM_INFO @ 3278.781967 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']
chip_sw_pwrmgr_sleep_wake_5_bug 24404941567564586547764956990920542613668261384416231075704465775869027507254 None
---- STDOUT ----
---- STDERR ----
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0 21104719193588722471639665457719535508763378543668530279756226869203037659365 None
---- STDERR ----
Another command (pid=358332) is running. Waiting for it to complete on the server (server_pid=279692)...
Another command (pid=412414) is running. Waiting for it to complete on the server (server_pid=279692)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_dev 16161194787334192746819445325416672049997777445165629606589254055184174862948 None
---- STDERR ----
Another command (pid=384039) is running. Waiting for it to complete on the server (server_pid=279692)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod 84077256750943752733010333301442644597104845127927230742647954879200377611592 None
Another command (pid=672792) is running. Waiting for it to complete on the server (server_pid=279692)...
Another command (pid=673621) is running. Waiting for it to complete on the server (server_pid=279692)...
Another command (pid=681098) is running. Waiting for it to complete on the server (server_pid=279692)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_prod_end 7341397489696926247624810576898680242334359008801623402596891015890268406771 None
Another command (pid=647885) is running. Waiting for it to complete on the server (server_pid=279692)...
Another command (pid=664336) is running. Waiting for it to complete on the server (server_pid=279692)...
Another command (pid=625147) is running. Waiting for it to complete on the server (server_pid=279692)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_good_rma 95297229117241564331719039469528548434339286374225678096553060364856662143392 None
Another command (pid=546466) is running. Waiting for it to complete on the server (server_pid=279692)...
Another command (pid=393512) is running. Waiting for it to complete on the server (server_pid=279692)...
Another command (pid=558631) is running. Waiting for it to complete on the server (server_pid=279692)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 34679715061898772899577415449874564946066622942977775924620119683986938282677 None
Another command (pid=572795) is running. Waiting for it to complete on the server (server_pid=279692)...
Another command (pid=607219) is running. Waiting for it to complete on the server (server_pid=279692)...
Another command (pid=564872) is running. Waiting for it to complete on the server (server_pid=279692)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_dev 3691472071524507000306097141043252065594264358096542435897600682751838140420 None
Another command (pid=522271) is running. Waiting for it to complete on the server (server_pid=279692)...
Another command (pid=520614) is running. Waiting for it to complete on the server (server_pid=279692)...
Another command (pid=402111) is running. Waiting for it to complete on the server (server_pid=279692)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod 42347285548015936356400444397768824549961118774259493986914254720703583723489 None
Another command (pid=435077) is running. Waiting for it to complete on the server (server_pid=279692)...
Another command (pid=384039) is running. Waiting for it to complete on the server (server_pid=279692)...
Another command (pid=437418) is running. Waiting for it to complete on the server (server_pid=279692)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_prod_end 53756381938187583043697243473988136498297428976058655503712300569549340804634 None
Another command (pid=450950) is running. Waiting for it to complete on the server (server_pid=279692)...
Another command (pid=370791) is running. Waiting for it to complete on the server (server_pid=279692)...
Another command (pid=550455) is running. Waiting for it to complete on the server (server_pid=279692)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_good_b_bad_rma 8808790947480999633593270399890973016266055531373176845482142958586269723691 None
Another command (pid=681098) is running. Waiting for it to complete on the server (server_pid=279692)...
Another command (pid=563601) is running. Waiting for it to complete on the server (server_pid=279692)...
Another command (pid=643414) is running. Waiting for it to complete on the server (server_pid=279692)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 53978596016727544529620029664454614951992215089038075015203204272452288339002 None
Another command (pid=402111) is running. Waiting for it to complete on the server (server_pid=279692)...
Another command (pid=450894) is running. Waiting for it to complete on the server (server_pid=279692)...
Another command (pid=550744) is running. Waiting for it to complete on the server (server_pid=279692)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_dev 5455657537906057855425490100000556990294001078379468333177026042290756796760 None
Another command (pid=383463) is running. Waiting for it to complete on the server (server_pid=279692)...
Another command (pid=596880) is running. Waiting for it to complete on the server (server_pid=279692)...
Another command (pid=424282) is running. Waiting for it to complete on the server (server_pid=279692)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod 21247912572321554784332901410739131460955049794860158071460726905341317476679 None
Another command (pid=573413) is running. Waiting for it to complete on the server (server_pid=279692)...
Another command (pid=577196) is running. Waiting for it to complete on the server (server_pid=279692)...
Another command (pid=522876) is running. Waiting for it to complete on the server (server_pid=279692)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_prod_end 2618393274378214315500122492282158774332531914280977335615105641183196320742 None
Another command (pid=450894) is running. Waiting for it to complete on the server (server_pid=279692)...
Another command (pid=550744) is running. Waiting for it to complete on the server (server_pid=279692)...
Another command (pid=549396) is running. Waiting for it to complete on the server (server_pid=279692)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_boot_policy_valid_a_bad_b_good_rma 5243144770232059284060956222846771742085822484747167884717924486026566401887 None
Another command (pid=563190) is running. Waiting for it to complete on the server (server_pid=279692)...
Another command (pid=546466) is running. Waiting for it to complete on the server (server_pid=279692)...
Another command (pid=393512) is running. Waiting for it to complete on the server (server_pid=279692)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_test_unlocked0 63568453916099546290277225604221282143919735824284635415645309043776642159616 None
Another command (pid=402111) is running. Waiting for it to complete on the server (server_pid=279692)...
Another command (pid=450950) is running. Waiting for it to complete on the server (server_pid=279692)...
Another command (pid=370791) is running. Waiting for it to complete on the server (server_pid=279692)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_dev 50016622026765332227776100508642846405306317028411571896993731218744289681815 None
Another command (pid=583264) is running. Waiting for it to complete on the server (server_pid=279692)...
Another command (pid=383463) is running. Waiting for it to complete on the server (server_pid=279692)...
Another command (pid=592030) is running. Waiting for it to complete on the server (server_pid=279692)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod 18102440709434114272162039815668320624745708867401202975574235501430092033626 None
---- STDERR ----
Another command (pid=358332) is running. Waiting for it to complete on the server (server_pid=279692)...
Another command (pid=412414) is running. Waiting for it to complete on the server (server_pid=279692)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_prod_end 74573028590696941907305292217658003416789627022080075267509855656128102145491 None
Another command (pid=370791) is running. Waiting for it to complete on the server (server_pid=279692)...
Another command (pid=550455) is running. Waiting for it to complete on the server (server_pid=279692)...
Another command (pid=450584) is running. Waiting for it to complete on the server (server_pid=279692)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_asm_init_rma 84182420458289431165617948712096255937287276997717205062054452128956974018150 None
Another command (pid=399641) is running. Waiting for it to complete on the server (server_pid=279692)...
Another command (pid=435077) is running. Waiting for it to complete on the server (server_pid=279692)...
Another command (pid=384039) is running. Waiting for it to complete on the server (server_pid=279692)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_volatile_raw_unlock 25709619246519165386468926763061291224503570998463870642988787924013588464445 None
---- STDERR ----
Another command (pid=358332) is running. Waiting for it to complete on the server (server_pid=279692)...
Another command (pid=412414) is running. Waiting for it to complete on the server (server_pid=279692)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_raw_unlock 7510754019603249427561677642472225918559413992730646694328804239868896988716 None
Another command (pid=608295) is running. Waiting for it to complete on the server (server_pid=279692)...
Another command (pid=611714) is running. Waiting for it to complete on the server (server_pid=279692)...
Another command (pid=612176) is running. Waiting for it to complete on the server (server_pid=279692)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
rom_e2e_self_hash 113843894819358004645444027625595537471183502069109073939060965343138774545208 None
---- STDERR ----
Another command (pid=358332) is running. Waiting for it to complete on the server (server_pid=279692)...
Another command (pid=412414) is running. Waiting for it to complete on the server (server_pid=279692)...
WARNING: Target pattern parsing failed.
ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
ERROR: Build did NOT complete successfully
_run_cmd -> had a non-zero return code of 1.
make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Error-[NOA] Null object access
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted 22541580404245703286074335944593048243217423959720944744516678608253700036033 327
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_test_unlocked0 30651622199829524391209398672617060587500728913953141009559177815051472668955 319
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_debug_dev 106333303685592857538322808414832908232539997873101495902395906232000238145310 352
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_dev 21087237978712185831643876022281403972621872277734429211713259368896690097335 303
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
rom_e2e_jtag_inject_rma 8490485782480046794885298999730010247262486970915471546984557254207417054248 310
src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078
The object at dereference depth 1 is being used before it was
constructed/allocated.
Please make sure that the object is allocated before using it.
UVM_ERROR @ * us: (cip_base_vseq.sv:649) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch
chip_rv_dm_lc_disabled 114718962036041396403538654441161784376661234384232010598128817257043305934069 215
UVM_INFO @ 1712.645011 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '(outstanding_load_resp | outstanding_store_resp)'
chip_sw_rv_core_ibex_lockstep_glitch 81188822845673252179403071005163399771788183773402533548578828123569230972880 319
UVM_ERROR @ 2580.041752 us: (ibex_core.sv:1014) [ASSERT FAILED] NoMemResponseWithoutPendingAccess
UVM_INFO @ 2580.041752 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_idle_load 105374997296388969492774499830981787908080976217102275132750473947584388702521 312
UVM_INFO @ 3518.157500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
chip_sw_power_sleep_load 101827998037434927816675077107903281738902193733777214195770981335865829209002 319
UVM_INFO @ 3900.714000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *
chip_sw_ast_clk_rst_inputs 44177124353465896293024699804366940478903133490428408502914031312856017322347 327
UVM_INFO @ 14677.393698 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 59689761611051724836281958762982300073219123955415884843424507666633344198313 363
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 99246557322469167705397916511283273593730852147418741134712825801250580625414 325
UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_dev 113165945370809243784867572385505406926277234238907162982647310252837330459101 365
UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_dev 97173306682912711637080562873344097280166798867569385433681147965191542710944 326
UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_bad_b_bad_prod 73686274025434937378992345979138166234287941372858150869630182410657882121936 367
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_prod_end 64042679883426891883919966030658045770013979560186941008345831907165046233328 368
UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_bad_rma 17269546614549465655754336089481936283856509401878472141731656798610761673894 368
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod 18623757215008327398878027036429715182661825174109430079053957452528581596375 326
UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_prod_end 28644359517326867844732697265597266199062111844281021813764283745767139851134 328
UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_bad_b_nothing_rma 97889904804180347761365004889412447570049738353032414238949916486912005793489 326
UVM_INFO @ 10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 99934963988032478392970128186875729965454445372254245108004592967866881571776 325
UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_dev 77314253593378590821353211145736796976989815129400051998256206311930541085241 328
UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode
rom_e2e_sigverify_always_a_nothing_b_bad_prod 49981406122636091936366412801252686253584523204514939396231157060634147264602 327
UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_prod_end 19883921761118007351073226149796563585787673501992433855718246689123250207830 327
UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rom_e2e_sigverify_always_a_nothing_b_bad_rma 60577473914734528961143450605037492242321886282628604807642666320324346986300 325
UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
rom_e2e_jtag_debug_rma 29915580656825876402486447205386711436509657754154941471542253198105933073407 330
UVM_INFO @ 14816.261680 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '$stable(key_data_i)'
rom_keymgr_functest 45002669703784787735218108880606095176191932519251827491167421172540990405594 327
UVM_ERROR @ 4777.621702 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M
UVM_INFO @ 4777.621702 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---