Simulation Results: edn/edn0

 
20/04/2026 17:21:27 DVSim: v1.32.0 sha: 8666f0e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.62 %
  • code
  • 82.01 %
  • assert
  • 96.31 %
  • func
  • 81.55 %
  • line
  • 97.66 %
  • branch
  • 92.47 %
  • cond
  • 86.83 %
  • toggle
  • 81.49 %
  • FSM
  • 51.61 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.020s 20.434us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.990s 43.842us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 1.120s 26.289us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.570s 57.740us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.210s 24.875us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.010s 46.961us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 1.120s 26.289us 1 1 100.00
edn_csr_aliasing 1.210s 24.875us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.510s 58.134us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.510s 58.134us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.510s 58.134us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.080s 27.942us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.110s 155.805us 1 1 100.00
errs 1 1 100.00
edn_err 1.060s 22.188us 1 1 100.00
disable 2 2 100.00
edn_disable 1.170s 47.673us 1 1 100.00
edn_disable_auto_req_mode 1.410s 33.880us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.670s 706.059us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 1.180s 54.340us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.830s 51.957us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.450s 189.537us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.450s 189.537us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.990s 43.842us 1 1 100.00
edn_csr_rw 1.120s 26.289us 1 1 100.00
edn_csr_aliasing 1.210s 24.875us 1 1 100.00
edn_same_csr_outstanding 1.290s 113.664us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.990s 43.842us 1 1 100.00
edn_csr_rw 1.120s 26.289us 1 1 100.00
edn_csr_aliasing 1.210s 24.875us 1 1 100.00
edn_same_csr_outstanding 1.290s 113.664us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 7.990s 520.511us 1 1 100.00
edn_tl_intg_err 1.980s 581.740us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.160s 16.872us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.110s 155.805us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.990s 520.511us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 7.990s 520.511us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 7.990s 520.511us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 7.990s 520.511us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.110s 155.805us 1 1 100.00
edn_sec_cm 7.990s 520.511us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.110s 155.805us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.980s 581.740us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 19.400s 6604.341us 1 1 100.00