Simulation Results: edn/edn1

 
20/04/2026 17:21:27 DVSim: v1.32.0 sha: 8666f0e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.83 %
  • code
  • 83.11 %
  • assert
  • 97.14 %
  • func
  • 80.25 %
  • line
  • 98.18 %
  • branch
  • 93.51 %
  • cond
  • 89.54 %
  • toggle
  • 87.74 %
  • FSM
  • 46.59 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.140s 18.069us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.850s 20.541us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.910s 16.371us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.090s 127.713us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.210s 231.940us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.130s 35.353us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.910s 16.371us 1 1 100.00
edn_csr_aliasing 1.210s 231.940us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.450s 50.710us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.450s 50.710us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.450s 50.710us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.780s 49.903us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.190s 28.630us 1 1 100.00
errs 1 1 100.00
edn_err 0.960s 28.825us 1 1 100.00
disable 2 2 100.00
edn_disable 0.800s 18.370us 1 1 100.00
edn_disable_auto_req_mode 1.020s 62.917us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.440s 272.151us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.700s 23.203us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.990s 58.544us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.230s 303.639us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.230s 303.639us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.850s 20.541us 1 1 100.00
edn_csr_rw 0.910s 16.371us 1 1 100.00
edn_csr_aliasing 1.210s 231.940us 1 1 100.00
edn_same_csr_outstanding 1.210s 113.790us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.850s 20.541us 1 1 100.00
edn_csr_rw 0.910s 16.371us 1 1 100.00
edn_csr_aliasing 1.210s 231.940us 1 1 100.00
edn_same_csr_outstanding 1.210s 113.790us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.990s 1103.346us 1 1 100.00
edn_tl_intg_err 1.290s 169.394us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.800s 27.649us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.190s 28.630us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.990s 1103.346us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.990s 1103.346us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.990s 1103.346us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.990s 1103.346us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.190s 28.630us 1 1 100.00
edn_sec_cm 3.990s 1103.346us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.190s 28.630us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.290s 169.394us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 20.300s 2810.514us 1 1 100.00