Simulation Results: entropy_src/rng_4bits

 
20/04/2026 17:21:27 DVSim: v1.32.0 sha: 8666f0e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 73.51 %
  • code
  • 86.43 %
  • assert
  • 83.09 %
  • func
  • 51.02 %
  • block
  • 94.29 %
  • line
  • 97.01 %
  • branch
  • 85.91 %
  • toggle
  • 76.33 %
  • FSM
  • 86.46 %
Validation stages
V1
83.33%
V2
93.75%
V2S
85.71%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 2.000s 30.772us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 24.000s 24.601us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 15.000s 19.881us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 32.000s 9852.251us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 27.000s 387.760us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
entropy_src_csr_mem_rw_with_rand_reset 21.000s 48.035us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 15.000s 19.881us 1 1 100.00
entropy_src_csr_aliasing 27.000s 387.760us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 2 3 66.67
entropy_src_smoke 2.000s 30.772us 1 1 100.00
entropy_src_rng 174.000s 9037.238us 1 1 100.00
entropy_src_fw_ov 45.000s 7543.098us 0 1 0.00
firmware_mode 0 1 0.00
entropy_src_fw_ov 45.000s 7543.098us 0 1 0.00
rng_mode 1 1 100.00
entropy_src_rng 174.000s 9037.238us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 213.000s 15037.695us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 174.000s 9037.238us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 174.000s 9037.238us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 174.000s 9037.238us 1 1 100.00
entropy_src_intr 20.000s 2043.731us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 174.000s 9037.238us 1 1 100.00
entropy_src_functional_alerts 15.000s 1534.184us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 289.000s 20167.198us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 13.000s 32.206us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 10.000s 1307.532us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 1.000s 18.143us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 25.000s 18.160us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 3.000s 61.151us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 3.000s 61.151us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 24.000s 24.601us 1 1 100.00
entropy_src_csr_rw 15.000s 19.881us 1 1 100.00
entropy_src_csr_aliasing 27.000s 387.760us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 129.251us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 24.000s 24.601us 1 1 100.00
entropy_src_csr_rw 15.000s 19.881us 1 1 100.00
entropy_src_csr_aliasing 27.000s 387.760us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 129.251us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 2.000s 55.019us 1 1 100.00
entropy_src_tl_intg_err 3.000s 72.395us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 174.000s 9037.238us 1 1 100.00
entropy_src_cfg_regwen 25.000s 19.521us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 174.000s 9037.238us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 174.000s 9037.238us 1 1 100.00
sec_cm_intersig_mubi 1 2 50.00
entropy_src_rng 174.000s 9037.238us 1 1 100.00
entropy_src_fw_ov 45.000s 7543.098us 0 1 0.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 13.000s 32.206us 1 1 100.00
entropy_src_sec_cm 2.000s 55.019us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 13.000s 32.206us 1 1 100.00
entropy_src_sec_cm 2.000s 55.019us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 174.000s 9037.238us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 13.000s 32.206us 1 1 100.00
entropy_src_sec_cm 2.000s 55.019us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 13.000s 32.206us 1 1 100.00
entropy_src_sec_cm 2.000s 55.019us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 13.000s 32.206us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 15.000s 1534.184us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 3.000s 72.395us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 72.000s 20064.907us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:354) scoreboard [scoreboard] alert recov_alert did not trigger max_delay:*
entropy_src_fw_ov 2169142748409115886744071775999198307070932408194025252076997742765356792749 800
UVM_INFO @ 7543097515 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (entropy_src_base_vseq.sv:83) virtual_sequencer [mirror] Failed to mirror extht_hi_total_fails
entropy_src_csr_mem_rw_with_rand_reset 26888366510321380655818232366658525042108730648249507609908764155669212423879 113
UVM_INFO @ 48035023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---