Simulation Results: flash_ctrl

 
20/04/2026 17:21:27 DVSim: v1.32.0 sha: 8666f0e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.47 %
  • code
  • 94.03 %
  • assert
  • 96.76 %
  • func
  • 95.63 %
  • line
  • 95.92 %
  • branch
  • 97.03 %
  • cond
  • 93.55 %
  • toggle
  • 97.93 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 48.620s 98.622us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 9.950s 54.272us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 10.700s 124.976us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 8.140s 41.925us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 41.410s 4481.668us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 20.900s 890.871us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 7.570s 53.865us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 8.140s 41.925us 1 1 100.00
flash_ctrl_csr_aliasing 20.900s 890.871us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 6.030s 17.659us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 5.750s 45.105us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 9.360s 26.406us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 33.460s 88.886us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1171.920s 178279.886us 1 1 100.00
flash_ctrl_hw_rma_reset 557.750s 40127.036us 1 1 100.00
flash_ctrl_lcmgr_intg 6.740s 39.292us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1296.820s 526050.167us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 132.580s 2476.161us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 6.150s 38.299us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 2021.290s 217974.536us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 37.430s 78.810us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 14.110s 30.146us 1 1 100.00
flash_ctrl_rw_evict_all_en 12.630s 50.741us 1 1 100.00
flash_ctrl_re_evict 16.960s 261.565us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 33.770s 129.533us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 33.770s 129.533us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 342.070s 45118.466us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 16.480s 438.446us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 339.410s 118.926us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 355.350s 6342.739us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 275.010s 1281.057us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 712.900s 594.450us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 6.390s 23.713us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 130.780s 2882.716us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 9.320s 37.386us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 5.340s 32.612us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 297.400s 296.682us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 69.730s 1397.021us 1 1 100.00
flash_ctrl_otp_reset 56.140s 125.332us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1171.920s 178279.886us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 126.150s 1571.251us 1 1 100.00
flash_ctrl_intr_wr 64.310s 12178.154us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 328.810s 131254.758us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 126.780s 43246.418us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 46.150s 3342.734us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 34.580s 1340.006us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 12.380s 27.436us 1 1 100.00
flash_ctrl_ro_derr 88.650s 1416.563us 1 1 100.00
flash_ctrl_rw_derr 180.700s 4002.791us 1 1 100.00
flash_ctrl_derr_detect 125.820s 3236.857us 1 1 100.00
flash_ctrl_integrity 433.730s 13996.532us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 9.360s 90.308us 1 1 100.00
flash_ctrl_ro_serr 87.240s 574.609us 1 1 100.00
flash_ctrl_rw_serr 161.220s 1956.580us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 42.370s 2958.878us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 51.020s 934.513us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 109.220s 8500.760us 1 1 100.00
flash_ctrl_write_word_sweep 7.090s 286.320us 1 1 100.00
flash_ctrl_read_word_sweep 6.500s 46.041us 1 1 100.00
flash_ctrl_ro 70.520s 2206.865us 1 1 100.00
flash_ctrl_rw 426.050s 16657.050us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 23.860s 697.660us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 548.370s 42012.838us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 36.980s 10063.829us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 5.810s 157.096us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 6.160s 30.540us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 7.080s 33.363us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 7.080s 33.363us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 10.700s 124.976us 1 1 100.00
flash_ctrl_csr_rw 8.140s 41.925us 1 1 100.00
flash_ctrl_csr_aliasing 20.900s 890.871us 1 1 100.00
flash_ctrl_same_csr_outstanding 6.930s 217.410us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 10.700s 124.976us 1 1 100.00
flash_ctrl_csr_rw 8.140s 41.925us 1 1 100.00
flash_ctrl_csr_aliasing 20.900s 890.871us 1 1 100.00
flash_ctrl_same_csr_outstanding 6.930s 217.410us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 30.440s 236.544us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 30.440s 236.544us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 30.440s 236.544us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 30.440s 236.544us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 28.790s 305.334us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_sec_cm 1558.390s 945.045us 1 1 100.00
flash_ctrl_tl_intg_err 177.590s 1865.135us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 177.590s 1865.135us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 177.590s 1865.135us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 14.290s 213.832us 1 1 100.00
flash_ctrl_wr_intg 6.060s 44.981us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 48.620s 98.622us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 56.140s 125.332us 1 1 100.00
flash_ctrl_disable 9.320s 37.386us 1 1 100.00
flash_ctrl_sec_info_access 34.170s 1808.505us 1 1 100.00
flash_ctrl_connect 5.340s 32.612us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 5.860s 22.989us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.140s 41.925us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 30.440s 236.544us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.140s 41.925us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 30.440s 236.544us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.140s 41.925us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 30.440s 236.544us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 9.320s 37.386us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 14.290s 213.832us 1 1 100.00
flash_ctrl_access_after_disable 5.540s 36.752us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 13.890s 43.454us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 9.320s 37.386us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 16.480s 438.446us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 426.050s 16657.050us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 161.220s 1956.580us 1 1 100.00
flash_ctrl_rw_derr 180.700s 4002.791us 1 1 100.00
flash_ctrl_integrity 433.730s 13996.532us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1171.920s 178279.886us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1558.390s 945.045us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1558.390s 945.045us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1558.390s 945.045us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1558.390s 945.045us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 8.000s 679.509us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 8.170s 51.802us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 6.690s 161.736us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1558.390s 945.045us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1558.390s 945.045us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1558.390s 945.045us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 18.690s 101.534us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 245.790s 482.135us 1 1 100.00