Simulation Results: hmac

 
20/04/2026 17:21:27 DVSim: v1.32.0 sha: 8666f0e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.00 %
  • code
  • 96.24 %
  • assert
  • 96.70 %
  • func
  • 44.07 %
  • line
  • 99.23 %
  • branch
  • 98.02 %
  • cond
  • 95.73 %
  • toggle
  • 100.00 %
  • FSM
  • 88.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 1.830s 407.083us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.900s 61.318us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.720s 41.859us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 10.680s 4381.003us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 4.260s 1478.331us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.170s 17.916us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.720s 41.859us 1 1 100.00
hmac_csr_aliasing 4.260s 1478.331us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 37.980s 5561.235us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 34.470s 846.089us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 8.380s 259.931us 1 1 100.00
hmac_test_sha384_vectors 331.630s 10521.954us 1 1 100.00
hmac_test_sha512_vectors 21.290s 228.425us 1 1 100.00
hmac_test_hmac256_vectors 6.810s 247.784us 1 1 100.00
hmac_test_hmac384_vectors 10.220s 329.343us 1 1 100.00
hmac_test_hmac512_vectors 10.000s 324.284us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 0.640s 18.827us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 661.460s 7375.152us 1 1 100.00
error 1 1 100.00
hmac_error 62.860s 12584.934us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 4.740s 789.600us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 1.830s 407.083us 1 1 100.00
hmac_long_msg 37.980s 5561.235us 1 1 100.00
hmac_back_pressure 34.470s 846.089us 1 1 100.00
hmac_datapath_stress 661.460s 7375.152us 1 1 100.00
hmac_burst_wr 0.640s 18.827us 1 1 100.00
hmac_stress_all 343.910s 9157.959us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 1.830s 407.083us 1 1 100.00
hmac_long_msg 37.980s 5561.235us 1 1 100.00
hmac_back_pressure 34.470s 846.089us 1 1 100.00
hmac_datapath_stress 661.460s 7375.152us 1 1 100.00
hmac_wipe_secret 4.740s 789.600us 1 1 100.00
hmac_test_sha256_vectors 8.380s 259.931us 1 1 100.00
hmac_test_sha384_vectors 331.630s 10521.954us 1 1 100.00
hmac_test_sha512_vectors 21.290s 228.425us 1 1 100.00
hmac_test_hmac256_vectors 6.810s 247.784us 1 1 100.00
hmac_test_hmac384_vectors 10.220s 329.343us 1 1 100.00
hmac_test_hmac512_vectors 10.000s 324.284us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 1.830s 407.083us 1 1 100.00
hmac_long_msg 37.980s 5561.235us 1 1 100.00
hmac_back_pressure 34.470s 846.089us 1 1 100.00
hmac_datapath_stress 661.460s 7375.152us 1 1 100.00
hmac_burst_wr 0.640s 18.827us 1 1 100.00
hmac_error 62.860s 12584.934us 1 1 100.00
hmac_wipe_secret 4.740s 789.600us 1 1 100.00
hmac_test_sha256_vectors 8.380s 259.931us 1 1 100.00
hmac_test_sha384_vectors 331.630s 10521.954us 1 1 100.00
hmac_test_sha512_vectors 21.290s 228.425us 1 1 100.00
hmac_test_hmac256_vectors 6.810s 247.784us 1 1 100.00
hmac_test_hmac384_vectors 10.220s 329.343us 1 1 100.00
hmac_test_hmac512_vectors 10.000s 324.284us 1 1 100.00
hmac_stress_all 343.910s 9157.959us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 343.910s 9157.959us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.770s 16.657us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.630s 13.313us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 1.970s 44.222us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 1.970s 44.222us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.900s 61.318us 1 1 100.00
hmac_csr_rw 0.720s 41.859us 1 1 100.00
hmac_csr_aliasing 4.260s 1478.331us 1 1 100.00
hmac_same_csr_outstanding 1.080s 87.141us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.900s 61.318us 1 1 100.00
hmac_csr_rw 0.720s 41.859us 1 1 100.00
hmac_csr_aliasing 4.260s 1478.331us 1 1 100.00
hmac_same_csr_outstanding 1.080s 87.141us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.810s 66.874us 1 1 100.00
hmac_tl_intg_err 2.760s 87.983us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.760s 87.983us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 1.830s 407.083us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 4.750s 449.475us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 110.030s 7541.949us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.050s 94.070us 1 1 100.00