Simulation Results

Simulation Results: i2c

20/04/2026 17:21:27 DVSim: v1.32.0 sha: 8666f0e json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
85.00 %

code
81.34 %

assert
96.19 %

func
77.48 %

line
96.41 %

branch
92.33 %

cond
84.67 %

toggle
89.24 %

FSM
44.05 %

Validation stages

V1		100.00%
V2		87.80%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	35.260s	1185.373us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	14.910s	5262.236us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.840s	32.731us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.840s	119.417us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	3.290s	116.093us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.640s	230.850us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	0.870s	23.727us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.840s	119.417us	1	1	100.00
	i2c_csr_aliasing	1.640s	230.850us	1	1	100.00

36/41 passed

87.80 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	0.920s	89.175us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	1850.340s	60967.322us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	51.120s	13781.518us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.750s	107.880us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	108.300s	5414.473us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	36.010s	2303.940us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	1.080s	592.931us	1	1	100.00
	i2c_host_fifo_fmt_empty	3.950s	247.112us	1	1	100.00
	i2c_host_fifo_reset_rx	6.250s	691.004us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	101.930s	4425.174us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	25.310s	1448.386us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	0.750s	14.759us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	2.230s	531.564us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	21.180s	16116.965us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	4.090s	1637.393us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	44.470s	1340.780us	1	1	100.00
	i2c_target_intr_smoke	4.610s	4060.531us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	0.970s	230.623us	1	1	100.00
	i2c_target_fifo_reset_tx	1.420s	610.226us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	622.700s	49731.664us	1	1	100.00
	i2c_target_stress_rd	44.470s	1340.780us	1	1	100.00
	i2c_target_intr_stress_wr	47.140s	26751.063us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	5.710s	6003.253us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	26.490s	2713.964us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	5.360s	4601.905us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	16.930s	10070.032us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	2.140s	2089.633us	1	1	100.00
	i2c_target_fifo_watermarks_tx	1.270s	617.189us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	51.120s	13781.518us	1	1	100.00
	i2c_host_perf_precise	180.850s	24410.751us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	25.310s	1448.386us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	4.380s	335.268us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	2.270s	2296.929us	1	1	100.00
	i2c_target_nack_acqfull_addr	2.500s	523.133us	1	1	100.00
	i2c_target_nack_txstretch	1.350s	1618.134us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	7.210s	651.789us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	1.520s	434.934us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.870s	25.836us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.750s	91.339us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	1.290s	95.044us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	1.290s	95.044us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.840s	32.731us	1	1	100.00
	i2c_csr_rw	0.840s	119.417us	1	1	100.00
	i2c_csr_aliasing	1.640s	230.850us	1	1	100.00
	i2c_same_csr_outstanding	1.190s	64.359us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.840s	32.731us	1	1	100.00
	i2c_csr_rw	0.840s	119.417us	1	1	100.00
	i2c_csr_aliasing	1.640s	230.850us	1	1	100.00
	i2c_same_csr_outstanding	1.190s	64.359us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	2.220s	113.025us	1	1	100.00
	i2c_sec_cm	1.320s	182.384us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	2.220s	113.025us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	11.330s	3075.607us	1
target_error_intr				1
	i2c_target_unexp_stop	0.720s	64.832us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	14.180s	2058.372us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between
	i2c_host_error_intr	74627438287421216240740052615267738398045235313371000514324650075193212171262	80	UVM_INFO @ 89175058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_stress_all	60673949146499557033767270634103645751164095220796121937084482053980855604708	132	UVM_INFO @ 60967321624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_mode_toggle	74397992478676546691242995908932184151696686073267859965679634020395935811150	81	UVM_INFO @ 14759279 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
	i2c_target_glitch	12298283500307723227166514916094854428101120322607077307386198436809380785595	84	UVM_INFO @ 531563549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])
	i2c_target_unexp_stop	74763850021287658663062112546733937192820074496629774777539260961830592714885	78	UVM_INFO @ 64832066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
	i2c_target_hrst	33825112523145842537072132082604612244087723683437156980749515514221934575857	79	UVM_INFO @ 10070032204 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
	i2c_host_stress_all_with_rand_reset	84646238918622465774206408555047405022057548633684018740248588034560700020489	84	UVM_INFO @ 3075606830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	20670148726211388191236744683185634364723547846743830791175486829173770364413	89	UVM_INFO @ 2058371619 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---