Simulation Results: kmac/unmasked

 
20/04/2026 17:21:27 DVSim: v1.32.0 sha: 8666f0e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.74 %
  • code
  • 88.83 %
  • assert
  • 97.75 %
  • func
  • 91.63 %
  • line
  • 97.23 %
  • branch
  • 94.95 %
  • cond
  • 94.11 %
  • toggle
  • 100.00 %
  • FSM
  • 57.85 %
Validation stages
V1
100.00%
V2
96.55%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 39.770s 6522.584us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 1.060s 83.562us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 0.970s 47.003us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 7.740s 1931.961us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 8.470s 558.137us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 1.960s 43.293us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 0.970s 47.003us 1 1 100.00
kmac_csr_aliasing 8.470s 558.137us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.820s 71.013us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.300s 59.469us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 1627.420s 22044.235us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 357.710s 15583.401us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 1772.680s 501095.260us 1 1 100.00
kmac_test_vectors_sha3_256 1531.240s 60414.995us 1 1 100.00
kmac_test_vectors_sha3_384 23.650s 6868.756us 1 1 100.00
kmac_test_vectors_sha3_512 12.190s 2216.760us 1 1 100.00
kmac_test_vectors_shake_128 186.970s 91259.965us 1 1 100.00
kmac_test_vectors_shake_256 1723.020s 86785.857us 1 1 100.00
kmac_test_vectors_kmac 2.430s 66.925us 1 1 100.00
kmac_test_vectors_kmac_xof 2.850s 308.045us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 49.470s 1158.666us 1 1 100.00
app 1 1 100.00
kmac_app 75.030s 5875.874us 1 1 100.00
app_with_partial_data 1 1 100.00
kmac_app_with_partial_data 219.820s 50065.254us 1 1 100.00
entropy_refresh 1 1 100.00
kmac_entropy_refresh 274.610s 72454.631us 1 1 100.00
error 1 1 100.00
kmac_error 107.240s 24738.494us 1 1 100.00
key_error 1 1 100.00
kmac_key_error 4.930s 1222.732us 1 1 100.00
sideload_invalid 0 1 0.00
kmac_sideload_invalid 57.320s 10035.352us 0 1 0.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 11.050s 649.643us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 17.490s 3522.620us 1 1 100.00
entropy_ready_error 1 1 100.00
kmac_entropy_ready_error 20.520s 15956.320us 1 1 100.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.270s 166.588us 1 1 100.00
stress_all 1 1 100.00
kmac_stress_all 179.170s 26599.664us 1 1 100.00
intr_test 1 1 100.00
kmac_intr_test 0.910s 16.726us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 0.940s 66.627us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 2.090s 104.899us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 2.090s 104.899us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 1.060s 83.562us 1 1 100.00
kmac_csr_rw 0.970s 47.003us 1 1 100.00
kmac_csr_aliasing 8.470s 558.137us 1 1 100.00
kmac_same_csr_outstanding 1.450s 68.935us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 1.060s 83.562us 1 1 100.00
kmac_csr_rw 0.970s 47.003us 1 1 100.00
kmac_csr_aliasing 8.470s 558.137us 1 1 100.00
kmac_same_csr_outstanding 1.450s 68.935us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.590s 333.950us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.590s 333.950us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.590s 333.950us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.590s 333.950us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 2.920s 737.731us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_sec_cm 17.690s 3038.503us 1 1 100.00
kmac_tl_intg_err 2.360s 142.639us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 2.360s 142.639us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.270s 166.588us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 39.770s 6522.584us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 49.470s 1158.666us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.590s 333.950us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 17.690s 3038.503us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 17.690s 3038.503us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 17.690s 3038.503us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 39.770s 6522.584us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.270s 166.588us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 17.690s 3038.503us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 1 1 100.00
kmac_mubi 189.120s 11195.878us 1 1 100.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 39.770s 6522.584us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
kmac_stress_all_with_rand_reset 45.790s 6022.164us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout kmac_reg_block.intr_state.kmac_done (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=3)
kmac_sideload_invalid 111062916551279705574992675657848920601353598186325475484881213902391525371501 79
UVM_INFO @ 10035351511 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---