Simulation Results: lc_ctrl/volatile_unlock_disabled

 
20/04/2026 17:21:27 DVSim: v1.32.0 sha: 8666f0e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.69 %
  • code
  • 84.16 %
  • assert
  • 94.13 %
  • func
  • 93.77 %
  • line
  • 97.17 %
  • branch
  • 93.82 %
  • cond
  • 79.10 %
  • toggle
  • 88.10 %
  • FSM
  • 62.62 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.950s 164.771us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.960s 299.997us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.810s 32.000us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.610s 38.002us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.360s 139.345us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.900s 20.176us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.810s 32.000us 1 1 100.00
lc_ctrl_csr_aliasing 1.360s 139.345us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 5.280s 55.095us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 9.430s 375.900us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.110s 41.440us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.150s 27.916us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.770s 380.440us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 8.790s 1511.137us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 7.770s 380.440us 1 1 100.00
lc_ctrl_prog_failure 1.150s 27.916us 1 1 100.00
lc_ctrl_errors 8.790s 1511.137us 1 1 100.00
lc_ctrl_security_escalation 6.650s 625.104us 1 1 100.00
lc_ctrl_jtag_state_failure 36.370s 17095.599us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.180s 192.871us 1 1 100.00
lc_ctrl_jtag_errors 61.490s 3458.114us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 2.580s 822.340us 1 1 100.00
lc_ctrl_jtag_state_post_trans 10.060s 1495.777us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.180s 192.871us 1 1 100.00
lc_ctrl_jtag_errors 61.490s 3458.114us 1 1 100.00
lc_ctrl_jtag_access 6.600s 1274.258us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 8.990s 868.983us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.440s 167.880us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.150s 129.545us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 15.030s 16005.233us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 5.540s 5460.567us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.090s 71.890us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.400s 86.685us 1 1 100.00
lc_ctrl_jtag_alert_test 1.370s 158.026us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 8.550s 474.383us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.270s 23.385us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 221.830s 20688.474us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.390s 144.397us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.740s 239.868us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.740s 239.868us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.960s 299.997us 1 1 100.00
lc_ctrl_csr_rw 0.810s 32.000us 1 1 100.00
lc_ctrl_csr_aliasing 1.360s 139.345us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.020s 152.978us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.960s 299.997us 1 1 100.00
lc_ctrl_csr_rw 0.810s 32.000us 1 1 100.00
lc_ctrl_csr_aliasing 1.360s 139.345us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.020s 152.978us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.000s 221.876us 1 1 100.00
lc_ctrl_tl_intg_err 1.480s 364.907us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.480s 364.907us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 9.430s 375.900us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.770s 380.440us 1 1 100.00
lc_ctrl_sec_cm 6.000s 221.876us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.770s 380.440us 1 1 100.00
lc_ctrl_sec_cm 6.000s 221.876us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.770s 380.440us 1 1 100.00
lc_ctrl_sec_cm 6.000s 221.876us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.770s 380.440us 1 1 100.00
lc_ctrl_sec_cm 6.000s 221.876us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.770s 380.440us 1 1 100.00
lc_ctrl_sec_cm 6.000s 221.876us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.770s 380.440us 1 1 100.00
lc_ctrl_sec_cm 6.000s 221.876us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.770s 380.440us 1 1 100.00
lc_ctrl_sec_cm 6.000s 221.876us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.770s 380.440us 1 1 100.00
lc_ctrl_sec_cm 6.000s 221.876us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.650s 625.104us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 5.280s 55.095us 1 1 100.00
lc_ctrl_jtag_state_post_trans 10.060s 1495.777us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.180s 325.469us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.180s 325.469us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 8.490s 3196.372us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.610s 2622.790us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.610s 2622.790us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 2.050s 137.197us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
lc_ctrl_stress_all_with_rand_reset 57074717714964236132778495289169696503436663991174534145655825490133766490000 198
UVM_INFO @ 137197063 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---