Simulation Results: lc_ctrl/volatile_unlock_enabled

 
20/04/2026 17:21:27 DVSim: v1.32.0 sha: 8666f0e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.10 %
  • code
  • 83.64 %
  • assert
  • 94.13 %
  • func
  • 92.53 %
  • line
  • 97.06 %
  • branch
  • 93.62 %
  • cond
  • 78.73 %
  • toggle
  • 87.12 %
  • FSM
  • 61.68 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.290s 125.327us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.850s 40.189us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.020s 16.067us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 2.440s 93.362us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.080s 29.384us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.380s 47.432us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.020s 16.067us 1 1 100.00
lc_ctrl_csr_aliasing 1.080s 29.384us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 4.120s 49.686us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 4.860s 1824.388us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.880s 23.166us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 1.420s 21.394us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 8.230s 1299.570us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 6.680s 1465.091us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 8.230s 1299.570us 1 1 100.00
lc_ctrl_prog_failure 1.420s 21.394us 1 1 100.00
lc_ctrl_errors 6.680s 1465.091us 1 1 100.00
lc_ctrl_security_escalation 9.280s 361.762us 1 1 100.00
lc_ctrl_jtag_state_failure 18.850s 6645.043us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.360s 1086.990us 1 1 100.00
lc_ctrl_jtag_errors 21.520s 7739.805us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 2.140s 484.990us 1 1 100.00
lc_ctrl_jtag_state_post_trans 10.710s 15433.161us 1 1 100.00
lc_ctrl_jtag_prog_failure 4.360s 1086.990us 1 1 100.00
lc_ctrl_jtag_errors 21.520s 7739.805us 1 1 100.00
lc_ctrl_jtag_access 4.770s 398.733us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 9.420s 973.581us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 3.160s 603.143us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.360s 40.770us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 10.310s 8995.833us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.890s 754.187us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.530s 224.854us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.310s 360.194us 1 1 100.00
lc_ctrl_jtag_alert_test 1.090s 71.572us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 5.040s 877.694us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.970s 17.360us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 179.040s 16740.393us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.010s 27.662us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.850s 54.312us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.850s 54.312us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.850s 40.189us 1 1 100.00
lc_ctrl_csr_rw 1.020s 16.067us 1 1 100.00
lc_ctrl_csr_aliasing 1.080s 29.384us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.990s 25.473us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.850s 40.189us 1 1 100.00
lc_ctrl_csr_rw 1.020s 16.067us 1 1 100.00
lc_ctrl_csr_aliasing 1.080s 29.384us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.990s 25.473us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.020s 123.224us 1 1 100.00
lc_ctrl_tl_intg_err 1.320s 192.298us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.320s 192.298us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 4.860s 1824.388us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 8.230s 1299.570us 1 1 100.00
lc_ctrl_sec_cm 6.020s 123.224us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 8.230s 1299.570us 1 1 100.00
lc_ctrl_sec_cm 6.020s 123.224us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.230s 1299.570us 1 1 100.00
lc_ctrl_sec_cm 6.020s 123.224us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.230s 1299.570us 1 1 100.00
lc_ctrl_sec_cm 6.020s 123.224us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 8.230s 1299.570us 1 1 100.00
lc_ctrl_sec_cm 6.020s 123.224us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.230s 1299.570us 1 1 100.00
lc_ctrl_sec_cm 6.020s 123.224us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.230s 1299.570us 1 1 100.00
lc_ctrl_sec_cm 6.020s 123.224us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 8.230s 1299.570us 1 1 100.00
lc_ctrl_sec_cm 6.020s 123.224us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 9.280s 361.762us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 4.120s 49.686us 1 1 100.00
lc_ctrl_jtag_state_post_trans 10.710s 15433.161us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.920s 709.751us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 4.920s 709.751us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 6.780s 822.356us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.270s 679.661us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 7.270s 679.661us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 4.610s 212.905us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (lc_ctrl_errors_vseq.sv:768) [lc_ctrl_lc_errors_vseq] Check failed nvm_rma_error_act == nvm_rma_error_exp (* [*] vs * [*])
lc_ctrl_stress_all_with_rand_reset 12903262171501415564749690488583346878215509342289690547420066435334558561832 1451
UVM_INFO @ 212905144 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---