Simulation Results: otbn

 
20/04/2026 17:21:27 DVSim: v1.32.0 sha: 8666f0e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 93.62 %
  • code
  • 94.55 %
  • assert
  • 89.29 %
  • func
  • 97.03 %
  • block
  • 99.36 %
  • line
  • 99.56 %
  • branch
  • 92.11 %
  • toggle
  • 89.09 %
  • FSM
  • 97.44 %
Validation stages
V1
100.00%
V2
100.00%
V2S
96.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 9.000s 39.484us 1 1 100.00
single_binary 1 1 100.00
otbn_single 7.000s 13.435us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 8.000s 23.156us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 4.000s 23.205us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 10.000s 814.185us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 7.000s 109.723us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 7.000s 36.051us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 4.000s 23.205us 1 1 100.00
otbn_csr_aliasing 7.000s 109.723us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 94.000s 12382.570us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 51.000s 10634.041us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 39.000s 98.201us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 48.000s 597.029us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 21.000s 161.196us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 27.000s 233.239us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 6.000s 86.209us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 7.000s 146.183us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 6.000s 26.663us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 9.000s 71.094us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 4.000s 15.632us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 6.000s 32.075us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 6.000s 32.075us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 8.000s 23.156us 1 1 100.00
otbn_csr_rw 4.000s 23.205us 1 1 100.00
otbn_csr_aliasing 7.000s 109.723us 1 1 100.00
otbn_same_csr_outstanding 5.000s 81.967us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 8.000s 23.156us 1 1 100.00
otbn_csr_rw 4.000s 23.205us 1 1 100.00
otbn_csr_aliasing 7.000s 109.723us 1 1 100.00
otbn_same_csr_outstanding 5.000s 81.967us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 11.000s 31.147us 1 1 100.00
otbn_dmem_err 8.000s 17.155us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 9.000s 532.643us 1 1 100.00
otbn_controller_ispr_rdata_err 9.000s 206.350us 1 1 100.00
otbn_mac_bignum_acc_err 10.000s 109.185us 1 1 100.00
otbn_urnd_err 5.000s 30.355us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 5.000s 9.865us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 5.000s 77.429us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 5.000s 28.186us 1 1 100.00
tl_intg_err 2 2 100.00
otbn_sec_cm 86.000s 2335.658us 1 1 100.00
otbn_tl_intg_err 10.000s 140.956us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 37.000s 680.354us 1 1 100.00
prim_fsm_check 1 1 100.00
otbn_sec_cm 86.000s 2335.658us 1 1 100.00
prim_count_check 1 1 100.00
otbn_sec_cm 86.000s 2335.658us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 9.000s 39.484us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 8.000s 17.155us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 11.000s 31.147us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 10.000s 140.956us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 6.000s 86.209us 1 1 100.00
sec_cm_controller_fsm_local_esc 5 5 100.00
otbn_imem_err 11.000s 31.147us 1 1 100.00
otbn_dmem_err 8.000s 17.155us 1 1 100.00
otbn_zero_state_err_urnd 7.000s 146.183us 1 1 100.00
otbn_illegal_mem_acc 5.000s 9.865us 1 1 100.00
otbn_sec_cm 86.000s 2335.658us 1 1 100.00
sec_cm_controller_fsm_sparse 1 1 100.00
otbn_sec_cm 86.000s 2335.658us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 7.000s 13.435us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 11.000s 31.147us 1 1 100.00
otbn_dmem_err 8.000s 17.155us 1 1 100.00
otbn_zero_state_err_urnd 7.000s 146.183us 1 1 100.00
otbn_illegal_mem_acc 5.000s 9.865us 1 1 100.00
otbn_sec_cm 86.000s 2335.658us 1 1 100.00
sec_cm_scramble_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 86.000s 2335.658us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 6.000s 86.209us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 5 5 100.00
otbn_imem_err 11.000s 31.147us 1 1 100.00
otbn_dmem_err 8.000s 17.155us 1 1 100.00
otbn_zero_state_err_urnd 7.000s 146.183us 1 1 100.00
otbn_illegal_mem_acc 5.000s 9.865us 1 1 100.00
otbn_sec_cm 86.000s 2335.658us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_sparse 1 1 100.00
otbn_sec_cm 86.000s 2335.658us 1 1 100.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 7.000s 13.435us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 6.000s 12.773us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 6.000s 36.133us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 59.000s 397.602us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 59.000s 397.602us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 0 1 0.00
otbn_rf_base_intg_err 9.000s 24.670us 0 1 0.00
sec_cm_rf_base_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 86.000s 2335.658us 1 1 100.00
sec_cm_stack_wr_ptr_ctr_redun 1 1 100.00
otbn_sec_cm 86.000s 2335.658us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 6.000s 53.930us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 1 1 100.00
otbn_sec_cm 86.000s 2335.658us 1 1 100.00
sec_cm_loop_stack_ctr_redun 1 1 100.00
otbn_sec_cm 86.000s 2335.658us 1 1 100.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 6.000s 158.895us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 6.000s 158.895us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 6.000s 17.105us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 7.000s 13.435us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 7.000s 13.435us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 7.000s 13.435us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 21.000s 161.196us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 7.000s 13.435us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 7.000s 13.435us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 8.000s 102.037us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 7.000s 13.435us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
otbn_sec_cm 86.000s 2335.658us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 38.000s 145.792us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 8.000s 28.108us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (otbn_rf_base_intg_err_vseq.sv:138) [otbn_rf_base_intg_err_vseq] Check failed (cfg.model_agent_cfg.vif.status == otbn_pkg::StatusLocked)
otbn_rf_base_intg_err 58601676767997770883848687950081833734481754691189678402588302979381931131632 123
UVM_INFO @ 24669775 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1237) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
otbn_stress_all_with_rand_reset 114522118494418247054742296452650711728932756183258814837515528654270357910040 181
UVM_INFO @ 145792355 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---