Simulation Results: otp_ctrl

 
20/04/2026 17:21:27 DVSim: v1.32.0 sha: 8666f0e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 78.85 %
  • code
  • 76.43 %
  • assert
  • 94.11 %
  • func
  • 66.01 %
  • line
  • 88.67 %
  • branch
  • 83.22 %
  • cond
  • 89.99 %
  • toggle
  • 77.04 %
  • FSM
  • 43.23 %
Validation stages
V1
100.00%
V2
85.00%
V2S
88.89%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.490s 203.176us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 4.060s 358.087us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.090s 1032.017us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.400s 75.489us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 5.360s 486.733us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 6.010s 669.264us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.090s 143.126us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.400s 75.489us 1 1 100.00
otp_ctrl_csr_aliasing 6.010s 669.264us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.260s 39.431us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.220s 62.520us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 16.280s 1538.334us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 4.850s 1740.387us 1 1 100.00
partition_check 1 2 50.00
otp_ctrl_background_chks 15.000s 8108.709us 0 1 0.00
otp_ctrl_check_fail 8.860s 2904.620us 1 1 100.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 3.780s 1997.161us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 4.420s 759.768us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 12.130s 419.364us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 7.550s 1411.333us 1 1 100.00
otp_ctrl_parallel_lc_esc 4.900s 754.085us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 22.250s 1462.234us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 5.760s 468.703us 0 1 0.00
test_access 1 1 100.00
otp_ctrl_test_access 20.780s 4899.310us 1 1 100.00
stress_all 0 1 0.00
otp_ctrl_stress_all 39.570s 6437.282us 0 1 0.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.480s 144.906us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 2.280s 76.927us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 4.790s 139.460us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 4.790s 139.460us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.090s 1032.017us 1 1 100.00
otp_ctrl_csr_rw 1.400s 75.489us 1 1 100.00
otp_ctrl_csr_aliasing 6.010s 669.264us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.770s 935.500us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.090s 1032.017us 1 1 100.00
otp_ctrl_csr_rw 1.400s 75.489us 1 1 100.00
otp_ctrl_csr_aliasing 6.010s 669.264us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.770s 935.500us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 112.470s 9346.604us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 112.470s 9346.604us 1 1 100.00
otp_ctrl_tl_intg_err 7.360s 745.210us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 112.470s 9346.604us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 112.470s 9346.604us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 7.360s 745.210us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 4.060s 358.087us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 4.060s 358.087us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 112.470s 9346.604us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 112.470s 9346.604us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 112.470s 9346.604us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 112.470s 9346.604us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 112.470s 9346.604us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 112.470s 9346.604us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 112.470s 9346.604us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 112.470s 9346.604us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 112.470s 9346.604us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 112.470s 9346.604us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 112.470s 9346.604us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 112.470s 9346.604us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 112.470s 9346.604us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 112.470s 9346.604us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 112.470s 9346.604us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 4.900s 754.085us 1 1 100.00
otp_ctrl_sec_cm 112.470s 9346.604us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.900s 754.085us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.900s 754.085us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 4.900s 754.085us 1 1 100.00
otp_ctrl_macro_errs 5.760s 468.703us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.900s 754.085us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 4.900s 754.085us 1 1 100.00
otp_ctrl_sec_cm 112.470s 9346.604us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 4.900s 754.085us 1 1 100.00
otp_ctrl_sec_cm 112.470s 9346.604us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.900s 754.085us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.900s 754.085us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 4.900s 754.085us 1 1 100.00
otp_ctrl_macro_errs 5.760s 468.703us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.900s 754.085us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 4.900s 754.085us 1 1 100.00
otp_ctrl_sec_cm 112.470s 9346.604us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 4.850s 1740.387us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 1 1 100.00
otp_ctrl_check_fail 8.860s 2904.620us 1 1 100.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 4.420s 759.768us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 4.420s 759.768us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 4.420s 759.768us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 4.420s 759.768us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 4.420s 759.768us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 4.060s 358.087us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 4.420s 759.768us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 4.060s 358.087us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 112.470s 9346.604us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 3.780s 1997.161us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 4.060s 358.087us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 4.060s 358.087us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 5.760s 468.703us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 7.770s 3051.236us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 7.950s 2605.684us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1315) [otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_check_error does not trigger!
otp_ctrl_background_chks 101179542402300852825282417775911898264888088579322627914924501944876442078216 5224
UVM_INFO @ 8108709058 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_stress_all 6123794641313761740954272257535314068898777583039450788898747622714642999959 48249
UVM_INFO @ 6437282011 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_*
otp_ctrl_macro_errs 41463387076647387014414505807763000353898988288364504841184080259494397030857 2960
UVM_INFO @ 468702584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = *
otp_ctrl_stress_all_with_rand_reset 45886056671262753493969670766354894515260970111992553009940414913865104703995 2171
UVM_INFO @ 2605684498 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---