Simulation Results: pwrmgr

 
20/04/2026 17:21:27 DVSim: v1.32.0 sha: 8666f0e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.86 %
  • code
  • 94.63 %
  • assert
  • 96.08 %
  • func
  • 96.87 %
  • line
  • 98.92 %
  • branch
  • 95.42 %
  • cond
  • 94.77 %
  • toggle
  • 90.02 %
  • FSM
  • 94.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
80.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.620s 24.815us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.710s 23.602us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.670s 21.959us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 2.110s 263.072us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.930s 125.937us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 1.030s 56.843us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.670s 21.959us 1 1 100.00
pwrmgr_csr_aliasing 0.930s 125.937us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.740s 168.770us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.740s 168.770us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.860s 97.585us 1 1 100.00
pwrmgr_lowpower_invalid 0.700s 173.789us 1 1 100.00
reset 2 2 100.00
pwrmgr_reset 0.660s 46.142us 1 1 100.00
pwrmgr_reset_invalid 0.910s 559.993us 1 1 100.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.660s 46.142us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.640s 75.608us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.700s 31.510us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.880s 156.112us 1 1 100.00
stress_all 1 1 100.00
pwrmgr_stress_all 3.770s 1021.806us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.600s 30.747us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.680s 56.403us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.680s 56.403us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.710s 23.602us 1 1 100.00
pwrmgr_csr_rw 0.670s 21.959us 1 1 100.00
pwrmgr_csr_aliasing 0.930s 125.937us 1 1 100.00
pwrmgr_same_csr_outstanding 0.680s 72.780us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.710s 23.602us 1 1 100.00
pwrmgr_csr_rw 0.670s 21.959us 1 1 100.00
pwrmgr_csr_aliasing 0.930s 125.937us 1 1 100.00
pwrmgr_same_csr_outstanding 0.680s 72.780us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
pwrmgr_tl_intg_err 0.650s 8.283us 0 1 0.00
pwrmgr_sec_cm 0.710s 6.276us 0 1 0.00
prim_count_check 0 1 0.00
pwrmgr_sec_cm 0.710s 6.276us 0 1 0.00
prim_fsm_check 0 1 0.00
pwrmgr_sec_cm 0.710s 6.276us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
pwrmgr_tl_intg_err 0.650s 8.283us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.940s 826.832us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 1 1 100.00
pwrmgr_wakeup_reset 0.640s 75.608us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 1.080s 102.072us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.660s 29.372us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 0 1 0.00
pwrmgr_sec_cm 0.710s 6.276us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
pwrmgr_sec_cm 0.710s 6.276us 0 1 0.00
sec_cm_fsm_terminal 0 1 0.00
pwrmgr_sec_cm 0.710s 6.276us 0 1 0.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.620s 33.879us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.600s 28.102us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.920s 249.800us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.670s 21.959us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.670s 21.959us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 0 1 0.00
pwrmgr_escalation_timeout 0.790s 358.071us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 5.560s 2475.023us 1 1 100.00

Error Messages

   Test seed line log context
Offending '((!clk_en) || status)'
pwrmgr_escalation_timeout 97993434737817837759745432428252580597391416719686903425450532204120882880692 79
UVM_ERROR @ 358070658 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 358070658 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [pwrmgr_common_vseq] expect alert:fatal_fault to fire
pwrmgr_tl_intg_err 28683815506277000324389280682222041688439390239273165667477345744168147971354 85
UVM_INFO @ 8282583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
pwrmgr_sec_cm 104781950311914095669021933746991860487866293450040168630579268124807798090331 78
UVM_INFO @ 6275929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---