Simulation Results: rom_ctrl/32kb

 
20/04/2026 17:21:27 DVSim: v1.32.0 sha: 8666f0e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.57 %
  • code
  • 94.92 %
  • assert
  • 96.95 %
  • func
  • 97.85 %
  • line
  • 99.59 %
  • branch
  • 99.64 %
  • cond
  • 95.99 %
  • toggle
  • 99.36 %
  • FSM
  • 80.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 4.920s 596.614us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 4.370s 933.035us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 3.690s 210.771us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 5.000s 2477.123us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 4.170s 131.478us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 4.610s 595.283us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 3.690s 210.771us 1 1 100.00
rom_ctrl_csr_aliasing 4.170s 131.478us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 4.220s 164.316us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 3.450s 561.654us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 1 1 100.00
rom_ctrl_max_throughput_chk 4.990s 179.599us 1 1 100.00
stress_all 1 1 100.00
rom_ctrl_stress_all 10.280s 331.580us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 7.260s 1173.458us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 3.060s 633.075us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 5.530s 137.238us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 5.530s 137.238us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.370s 933.035us 1 1 100.00
rom_ctrl_csr_rw 3.690s 210.771us 1 1 100.00
rom_ctrl_csr_aliasing 4.170s 131.478us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.330s 168.104us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 4.370s 933.035us 1 1 100.00
rom_ctrl_csr_rw 3.690s 210.771us 1 1 100.00
rom_ctrl_csr_aliasing 4.170s 131.478us 1 1 100.00
rom_ctrl_same_csr_outstanding 4.330s 168.104us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 16.670s 531.784us 0 1 0.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 11.660s 1824.551us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 193.410s 4242.705us 1 1 100.00
rom_ctrl_tl_intg_err 22.160s 1599.803us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 193.410s 4242.705us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 193.410s 4242.705us 1 1 100.00
sec_cm_checker_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 16.670s 531.784us 0 1 0.00
sec_cm_checker_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 16.670s 531.784us 0 1 0.00
sec_cm_checker_fsm_local_esc 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 16.670s 531.784us 0 1 0.00
sec_cm_compare_ctrl_flow_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 16.670s 531.784us 0 1 0.00
sec_cm_compare_ctr_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 16.670s 531.784us 0 1 0.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 193.410s 4242.705us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 193.410s 4242.705us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 4.920s 596.614us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 4.920s 596.614us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 4.920s 596.614us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 22.160s 1599.803us 1 1 100.00
sec_cm_bus_local_esc 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 16.670s 531.784us 0 1 0.00
rom_ctrl_kmac_err_chk 7.260s 1173.458us 1 1 100.00
sec_cm_mux_mubi 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 16.670s 531.784us 0 1 0.00
sec_cm_mux_consistency 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 16.670s 531.784us 0 1 0.00
sec_cm_ctrl_redun 0 1 0.00
rom_ctrl_corrupt_sig_fatal_chk 16.670s 531.784us 0 1 0.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 11.660s 1824.551us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 193.410s 4242.705us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 126.700s 4890.604us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_corrupt_sig_fatal_chk_vseq.sv:149) [rom_ctrl_corrupt_sig_fatal_chk_vseq] Check failed (cfg.rom_ctrl_vif.pwrmgr_data.done != MuBi4True)
rom_ctrl_corrupt_sig_fatal_chk 61062343798941384373628871799265093388448226587715757283590495759675018511537 80
UVM_INFO @ 531784225 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---