Simulation Results: rv_timer

 
20/04/2026 17:21:27 DVSim: v1.32.0 sha: 8666f0e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.98 %
  • code
  • 100.00 %
  • assert
  • 96.82 %
  • func
  • 94.12 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 1.170s 1064.431us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.620s 21.456us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.590s 41.497us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 3.120s 407.357us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.760s 153.391us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.890s 19.812us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.590s 41.497us 1 1 100.00
rv_timer_csr_aliasing 0.760s 153.391us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 0.730s 218.586us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 1.390s 903.419us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 158.050s 214465.461us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 158.050s 214465.461us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 2.880s 3748.176us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.570s 12.607us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.550s 22.248us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 2.020s 474.325us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 2.020s 474.325us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.620s 21.456us 1 1 100.00
rv_timer_csr_rw 0.590s 41.497us 1 1 100.00
rv_timer_csr_aliasing 0.760s 153.391us 1 1 100.00
rv_timer_same_csr_outstanding 0.720s 16.065us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.620s 21.456us 1 1 100.00
rv_timer_csr_rw 0.590s 41.497us 1 1 100.00
rv_timer_csr_aliasing 0.760s 153.391us 1 1 100.00
rv_timer_same_csr_outstanding 0.720s 16.065us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.760s 64.616us 1 1 100.00
rv_timer_tl_intg_err 1.060s 92.573us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.060s 92.573us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 0.600s 56.262us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 0.670s 58.282us 0 1 0.00
stress_all_with_rand_reset 0 1 0.00
rv_timer_stress_all_with_rand_reset 0.610s 34.692us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == *
rv_timer_min 53526378726523515509289425789784521963386908961211042078455054770532689687024 75
UVM_INFO @ 56262140 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 113343956998977903801886583373727362563664396403228937146558586906636118650809 77
UVM_INFO @ 218585760 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*])
rv_timer_max 56992818119996399962840088831199926296382898822028284492281759178880557613359 75
UVM_INFO @ 58282399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1170) [rv_timer_common_vseq] Check failed (vseq_done)
rv_timer_stress_all_with_rand_reset 52218713716678884807674922850651514101500369138853245316027478858719637288309 79
UVM_INFO @ 34691723 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---