Simulation Results: spi_device/2p

 
20/04/2026 17:21:27 DVSim: v1.32.0 sha: 8666f0e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 87.34 %
  • code
  • 94.15 %
  • assert
  • 94.62 %
  • func
  • 73.26 %
  • line
  • 99.16 %
  • branch
  • 98.46 %
  • cond
  • 96.04 %
  • toggle
  • 87.74 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 171.810s 32866.742us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 1.330s 155.582us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 1.380s 190.639us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 16.340s 365.136us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 6.660s 480.414us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 1.530s 56.920us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 1.380s 190.639us 1 1 100.00
spi_device_csr_aliasing 6.660s 480.414us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.670s 10.779us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.410s 29.529us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.900s 56.370us 1 1 100.00
mem_parity 1 1 100.00
spi_device_mem_parity 0.920s 25.446us 1 1 100.00
mem_cfg 1 1 100.00
spi_device_ram_cfg 0.720s 36.002us 1 1 100.00
tpm_read 1 1 100.00
spi_device_tpm_rw 1.280s 72.119us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 1.280s 72.119us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 1.940s 3023.399us 1 1 100.00
spi_device_tpm_sts_read 0.750s 17.823us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 18.830s 4639.641us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 5.030s 2611.990us 1 1 100.00
spi_device_flash_all 8.030s 1721.094us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 4.030s 5229.930us 1 1 100.00
spi_device_flash_all 8.030s 1721.094us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 4.030s 5229.930us 1 1 100.00
spi_device_flash_all 8.030s 1721.094us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 8.030s 1721.094us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 5.600s 4023.759us 1 1 100.00
spi_device_flash_all 8.030s 1721.094us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 5.600s 4023.759us 1 1 100.00
spi_device_flash_all 8.030s 1721.094us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 5.600s 4023.759us 1 1 100.00
spi_device_flash_all 8.030s 1721.094us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 5.600s 4023.759us 1 1 100.00
spi_device_flash_all 8.030s 1721.094us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 5.600s 4023.759us 1 1 100.00
spi_device_flash_all 8.030s 1721.094us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 5.840s 620.841us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 19.840s 7350.940us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 19.840s 7350.940us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 19.840s 7350.940us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 6.830s 315.602us 1 1 100.00
spi_device_read_buffer_direct 3.060s 394.997us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 19.840s 7350.940us 1 1 100.00
spi_device_flash_all 8.030s 1721.094us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 8.030s 1721.094us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 8.030s 1721.094us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 2.030s 249.340us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 2.030s 249.340us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 171.810s 32866.742us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 210.460s 267193.853us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 275.670s 44071.206us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.740s 13.122us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 1.020s 12.048us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 3.170s 65.968us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 3.170s 65.968us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 1.330s 155.582us 1 1 100.00
spi_device_csr_rw 1.380s 190.639us 1 1 100.00
spi_device_csr_aliasing 6.660s 480.414us 1 1 100.00
spi_device_same_csr_outstanding 3.190s 94.930us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 1.330s 155.582us 1 1 100.00
spi_device_csr_rw 1.380s 190.639us 1 1 100.00
spi_device_csr_aliasing 6.660s 480.414us 1 1 100.00
spi_device_same_csr_outstanding 3.190s 94.930us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 1.000s 220.177us 1 1 100.00
spi_device_tl_intg_err 17.050s 4980.431us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 17.050s 4980.431us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
spi_device_flash_mode_ignore_cmds 994.360s 1500000.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue
spi_device_flash_mode_ignore_cmds 68949465262253628168539557523879479523963887439798866426018433939186545227855 97
UVM_INFO @ 1500000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---