Simulation Results: spi_host

 
20/04/2026 17:21:27 DVSim: v1.32.0 sha: 8666f0e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.97 %
  • code
  • 94.62 %
  • assert
  • 95.64 %
  • func
  • 88.66 %
  • block
  • 96.69 %
  • line
  • 98.76 %
  • branch
  • 92.75 %
  • toggle
  • 86.98 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 21.000s 2213.429us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 23.799us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 55.977us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 3.000s 162.662us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 32.905us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 1.000s 25.089us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 55.977us 1 1 100.00
spi_host_csr_aliasing 1.000s 32.905us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 23.810us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 2.000s 16.964us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 2.000s 67.876us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 3.000s 89.745us 1 1 100.00
spi_host_error_cmd 2.000s 60.224us 1 1 100.00
spi_host_event 7.000s 1275.512us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 2.000s 64.414us 1 1 100.00
speed 1 1 100.00
spi_host_speed 2.000s 64.414us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 2.000s 64.414us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 2.000s 86.383us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 24.804us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 2.000s 64.414us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 2.000s 64.414us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 21.000s 2213.429us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 21.000s 2213.429us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 2.000s 42.029us 1 1 100.00
spien 1 1 100.00
spi_host_spien 6.000s 453.156us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 568.000s 21057.420us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 3.000s 97.794us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 3.000s 89.745us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 1.000s 26.177us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 42.671us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 2.000s 237.248us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 2.000s 237.248us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 23.799us 1 1 100.00
spi_host_csr_rw 1.000s 55.977us 1 1 100.00
spi_host_csr_aliasing 1.000s 32.905us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 46.855us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 23.799us 1 1 100.00
spi_host_csr_rw 1.000s 55.977us 1 1 100.00
spi_host_csr_aliasing 1.000s 32.905us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 46.855us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 2.000s 85.218us 1 1 100.00
spi_host_sec_cm 1.000s 246.100us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 85.218us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
spi_host_upper_range_clkdiv 96.000s 5680.967us 1 1 100.00