Simulation Results: sram_ctrl/main

 
20/04/2026 17:21:27 DVSim: v1.32.0 sha: 8666f0e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.01 %
  • code
  • 95.92 %
  • assert
  • 96.32 %
  • func
  • 92.80 %
  • block
  • 94.93 %
  • line
  • 95.55 %
  • branch
  • 92.06 %
  • toggle
  • 96.09 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
90.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 5.000s 1134.888us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 32.842us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 33.247us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 29.548us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 17.970us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 3.000s 963.920us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 33.247us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 17.970us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 214.000s 29433.566us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 45.000s 3283.456us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 17.000s 3375.521us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 310.000s 63207.565us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 142.000s 12380.497us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 7.000s 1346.427us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 41.000s 25851.018us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 26.000s 5722.383us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 4.000s 1374.103us 1 1 100.00
sram_ctrl_partial_access_b2b 128.000s 12802.060us 1 1 100.00
max_throughput 1 3 33.33
sram_ctrl_max_throughput 5.000s 2738.190us 0 1 0.00
sram_ctrl_throughput_w_partial_write 6.000s 2796.869us 1 1 100.00
sram_ctrl_throughput_w_readback 4.000s 1026.853us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 4.000s 721.747us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 3.000s 1972.708us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 80.000s 21255.095us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 75.083us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 157.549us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 157.549us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 32.842us 1 1 100.00
sram_ctrl_csr_rw 1.000s 33.247us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 17.970us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 64.798us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 32.842us 1 1 100.00
sram_ctrl_csr_rw 1.000s 33.247us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 17.970us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 64.798us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 24.000s 7421.393us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 5.000s 1425.548us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 163.901us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 5.000s 1425.548us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 163.901us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 4.000s 721.747us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 4.000s 721.747us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 33.247us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 26.000s 5722.383us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 26.000s 5722.383us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 26.000s 5722.383us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 41.000s 25851.018us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 4.000s 669.666us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 24.000s 7421.393us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 6.000s 681.406us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 5.000s 1134.888us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 5.000s 1134.888us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 26.000s 5722.383us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 5.000s 1425.548us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 41.000s 25851.018us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 5.000s 1425.548us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 5.000s 1425.548us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 5.000s 1134.888us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 5.000s 1425.548us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 7.000s 293.543us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (sram_ctrl_base_vseq.sv:329) [sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-*:*], *'b0}) <= *; mask dist {'* :/ * - partial_access_pct, [* : '* - *] :/ partial_access_pct};}) Randomization failed!
sram_ctrl_max_throughput 821587165789471275542014916002767005128390886837789970397966112018608139642 102
UVM_INFO @ 2738189837 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 18523820912559083247174267266175111916617137914059726713512118064373877402230 102
UVM_INFO @ 1026852930 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---