Simulation Results: sram_ctrl/ret

 
20/04/2026 17:21:27 DVSim: v1.32.0 sha: 8666f0e json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.24 %
  • code
  • 83.29 %
  • assert
  • 96.43 %
  • func
  • 94.00 %
  • block
  • 93.73 %
  • line
  • 94.89 %
  • branch
  • 89.51 %
  • toggle
  • 82.08 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
90.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 1.000s 151.105us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 46.399us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 2.000s 18.608us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 183.778us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 67.119us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 84.350us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 2.000s 18.608us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 67.119us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 9.000s 1838.529us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 3.000s 207.322us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 2.000s 36.897us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 167.000s 3901.856us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 7.000s 1627.441us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 19.000s 3082.116us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 4.000s 449.151us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 8.000s 709.727us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 31.701us 1 1 100.00
sram_ctrl_partial_access_b2b 201.000s 11985.504us 1 1 100.00
max_throughput 1 3 33.33
sram_ctrl_max_throughput 1.000s 91.597us 0 1 0.00
sram_ctrl_throughput_w_partial_write 2.000s 123.447us 1 1 100.00
sram_ctrl_throughput_w_readback 1.000s 24.479us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 8.000s 7626.575us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.000s 34.342us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 17.000s 15973.010us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 12.252us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 110.803us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 110.803us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 46.399us 1 1 100.00
sram_ctrl_csr_rw 2.000s 18.608us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 67.119us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 45.144us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 46.399us 1 1 100.00
sram_ctrl_csr_rw 2.000s 18.608us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 67.119us 1 1 100.00
sram_ctrl_same_csr_outstanding 1.000s 45.144us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 1540.194us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 1020.724us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 676.727us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 1020.724us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 676.727us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 8.000s 7626.575us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 8.000s 7626.575us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 2.000s 18.608us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 8.000s 709.727us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 8.000s 709.727us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 8.000s 709.727us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 4.000s 449.151us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 1.000s 37.943us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 4.000s 1540.194us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 1.000s 40.981us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 1.000s 151.105us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 1.000s 151.105us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 8.000s 709.727us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 1020.724us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 4.000s 449.151us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 1020.724us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 1020.724us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 1.000s 151.105us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 1020.724us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 54.000s 11055.387us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (sram_ctrl_base_vseq.sv:329) [sram_ctrl_throughput_vseq] Check failed (std::randomize(mask) with {$countones(mask ^ {mask[bus_params_pkg::BUS_DBW-*:*], *'b0}) <= *; mask dist {'* :/ * - partial_access_pct, [* : '* - *] :/ partial_access_pct};}) Randomization failed!
sram_ctrl_max_throughput 73661343814109488701883855545290670484218151952888780457131445904482787579143 102
UVM_INFO @ 91597201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_readback 41129385482968936318495439471311198029721785587867507611116685206103890575841 102
UVM_INFO @ 24478911 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---