Simulation Results: uart

 
20/04/2026 17:21:27 DVSim: v1.32.0 sha: 8666f0e json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.17 %
  • code
  • 95.87 %
  • assert
  • 97.12 %
  • func
  • 50.53 %
  • line
  • 99.17 %
  • branch
  • 97.44 %
  • cond
  • 95.33 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 1.490s 691.743us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.880s 14.879us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.850s 51.957us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 2.270s 699.070us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.770s 233.225us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 1.300s 113.008us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.850s 51.957us 1 1 100.00
uart_csr_aliasing 0.770s 233.225us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 136.500s 125829.874us 1 1 100.00
parity 2 2 100.00
uart_smoke 1.490s 691.743us 1 1 100.00
uart_tx_rx 136.500s 125829.874us 1 1 100.00
parity_error 2 2 100.00
uart_intr 141.700s 201611.241us 1 1 100.00
uart_rx_parity_err 36.540s 28361.838us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 136.500s 125829.874us 1 1 100.00
uart_intr 141.700s 201611.241us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 129.440s 115586.010us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 169.000s 113461.001us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 75.520s 70312.124us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 141.700s 201611.241us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 141.700s 201611.241us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 141.700s 201611.241us 1 1 100.00
perf 1 1 100.00
uart_perf 771.250s 20250.183us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 8.470s 8192.649us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 8.470s 8192.649us 1 1 100.00
rx_noise_filter 1 1 100.00
uart_noise_filter 21.790s 21645.123us 1 1 100.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 68.600s 82009.663us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 1.530s 577.112us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 37.630s 5937.811us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 295.770s 66891.007us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 160.680s 304006.591us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.730s 22.076us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.790s 16.380us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.930s 403.011us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.930s 403.011us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.880s 14.879us 1 1 100.00
uart_csr_rw 0.850s 51.957us 1 1 100.00
uart_csr_aliasing 0.770s 233.225us 1 1 100.00
uart_same_csr_outstanding 0.770s 21.611us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.880s 14.879us 1 1 100.00
uart_csr_rw 0.850s 51.957us 1 1 100.00
uart_csr_aliasing 0.770s 233.225us 1 1 100.00
uart_same_csr_outstanding 0.770s 21.611us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.890s 159.523us 1 1 100.00
uart_tl_intg_err 1.370s 82.579us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.370s 82.579us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 13.570s 6745.974us 1 1 100.00