Simulation Results: adc_ctrl

 
21/04/2026 00:01:59 DVSim: v1.32.0 sha: 089baca json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 65.38 %
  • code
  • 92.17 %
  • assert
  • 90.92 %
  • func
  • 13.04 %
  • line
  • 97.97 %
  • branch
  • 96.35 %
  • cond
  • 85.94 %
  • toggle
  • 99.53 %
  • FSM
  • 81.08 %
Validation stages
V1
100.00%
V2
52.63%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 5.480s 5939.378us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 2.530s 1163.701us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 1.000s 495.404us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 29.770s 52804.160us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 2.120s 583.298us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.360s 349.386us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 1.000s 495.404us 1 1 100.00
adc_ctrl_csr_aliasing 2.120s 583.298us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 0 1 0.00
adc_ctrl_filters_polled 0.760s 411.813us 0 1 0.00
filters_polled_fixed 0 1 0.00
adc_ctrl_filters_polled_fixed 1.450s 324.827us 0 1 0.00
filters_interrupt 0 1 0.00
adc_ctrl_filters_interrupt 1.450s 490.095us 0 1 0.00
filters_interrupt_fixed 0 1 0.00
adc_ctrl_filters_interrupt_fixed 1.070s 350.276us 0 1 0.00
filters_wakeup 0 1 0.00
adc_ctrl_filters_wakeup 1.240s 465.047us 0 1 0.00
filters_wakeup_fixed 0 1 0.00
adc_ctrl_filters_wakeup_fixed 0.750s 331.428us 0 1 0.00
filters_both 0 1 0.00
adc_ctrl_filters_both 0.990s 457.282us 0 1 0.00
clock_gating 0 1 0.00
adc_ctrl_clock_gating 1.500s 431.773us 0 1 0.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 3.840s 4621.363us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 12.530s 27725.033us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 142.530s 75350.552us 1 1 100.00
stress_all 0 1 0.00
adc_ctrl_stress_all 0.920s 662.900us 0 1 0.00
alert_test 1 1 100.00
adc_ctrl_alert_test 1.530s 461.722us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 0.770s 335.624us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 2.160s 623.250us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 2.160s 623.250us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 2.530s 1163.701us 1 1 100.00
adc_ctrl_csr_rw 1.000s 495.404us 1 1 100.00
adc_ctrl_csr_aliasing 2.120s 583.298us 1 1 100.00
adc_ctrl_same_csr_outstanding 6.460s 2237.750us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 2.530s 1163.701us 1 1 100.00
adc_ctrl_csr_rw 1.000s 495.404us 1 1 100.00
adc_ctrl_csr_aliasing 2.120s 583.298us 1 1 100.00
adc_ctrl_same_csr_outstanding 6.460s 2237.750us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 8.000s 3836.188us 1 1 100.00
adc_ctrl_tl_intg_err 6.070s 8934.791us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 6.070s 8934.791us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
adc_ctrl_stress_all_with_rand_reset 13.470s 20683.326us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [*, *]
adc_ctrl_filters_polled 72535893726184187329108703233233544847323817479523517065279590821151242378597 389
UVM_INFO @ 411813476 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 4630944701592001278120756443729869131368694603249235393180510541447763358360 389
UVM_INFO @ 324826808 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 137132083485364844631645994939040774937279312400817171952341613421504269328 389
UVM_INFO @ 490095453 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 5969172045005262068351133214208556042430664781053176567812367928057071034367 389
UVM_INFO @ 350275579 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 72021240076048035359870950677443850098588866461670553562089173921959685074224 389
UVM_INFO @ 465047175 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 23778787747461437546177870186263311386348747558745952689591204122013786266359 389
UVM_INFO @ 331427855 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 12086222349749752362390774626453896023117929324892796550971722152475104231126 389
UVM_INFO @ 431772732 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 7343252186260452071624572697297979110920479653183281026314710906219168256496 389
UVM_INFO @ 457282022 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 17993941564596803489275709090535073135402828856125495069228365830634857820531 475
UVM_INFO @ 20683326137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 29094321047490357319403475819503277925954084053064772028064432456562028765773 390
UVM_INFO @ 662900067 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---