Simulation Results: aes/masked

 
21/04/2026 00:01:59 DVSim: v1.32.0 sha: 089baca json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.73 %
  • code
  • 95.24 %
  • assert
  • 98.29 %
  • func
  • 66.67 %
  • block
  • 95.91 %
  • line
  • 97.63 %
  • branch
  • 89.80 %
  • toggle
  • 98.05 %
  • FSM
  • 95.48 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 109.135us 1 1 100.00
smoke 1 1 100.00
aes_smoke 6.000s 258.686us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 80.078us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 81.656us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 5.000s 324.963us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 3.000s 152.047us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 191.725us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 81.656us 1 1 100.00
aes_csr_aliasing 3.000s 152.047us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 6.000s 258.686us 1 1 100.00
aes_config_error 3.000s 87.728us 1 1 100.00
aes_stress 5.000s 252.501us 1 1 100.00
key_length 3 3 100.00
aes_smoke 6.000s 258.686us 1 1 100.00
aes_config_error 3.000s 87.728us 1 1 100.00
aes_stress 5.000s 252.501us 1 1 100.00
back2back 2 2 100.00
aes_stress 5.000s 252.501us 1 1 100.00
aes_b2b 21.000s 692.755us 1 1 100.00
backpressure 1 1 100.00
aes_stress 5.000s 252.501us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 6.000s 258.686us 1 1 100.00
aes_config_error 3.000s 87.728us 1 1 100.00
aes_stress 5.000s 252.501us 1 1 100.00
aes_alert_reset 12.000s 4742.994us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 3.000s 57.546us 1 1 100.00
aes_config_error 3.000s 87.728us 1 1 100.00
aes_alert_reset 12.000s 4742.994us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 4.000s 284.051us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 13.000s 315.195us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 9.000s 218.395us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 12.000s 4742.994us 1 1 100.00
stress 1 1 100.00
aes_stress 5.000s 252.501us 1 1 100.00
sideload 2 2 100.00
aes_stress 5.000s 252.501us 1 1 100.00
aes_sideload 4.000s 99.624us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 95.533us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 11.000s 142.029us 1 1 100.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 4.000s 115.815us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 3.000s 176.758us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 240.020us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 240.020us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 80.078us 1 1 100.00
aes_csr_rw 1.000s 81.656us 1 1 100.00
aes_csr_aliasing 3.000s 152.047us 1 1 100.00
aes_same_csr_outstanding 2.000s 72.046us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 80.078us 1 1 100.00
aes_csr_rw 1.000s 81.656us 1 1 100.00
aes_csr_aliasing 3.000s 152.047us 1 1 100.00
aes_same_csr_outstanding 2.000s 72.046us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 4.000s 85.002us 1 1 100.00
fault_inject 3 3 100.00
aes_fi 2.000s 114.635us 1 1 100.00
aes_control_fi 2.000s 50.917us 1 1 100.00
aes_cipher_fi 2.000s 46.979us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 183.550us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 183.550us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 183.550us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 183.550us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 292.271us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 4.000s 1176.041us 1 1 100.00
aes_tl_intg_err 4.000s 1021.350us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 4.000s 1021.350us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 12.000s 4742.994us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 183.550us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 183.550us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 6.000s 258.686us 1 1 100.00
aes_stress 5.000s 252.501us 1 1 100.00
aes_alert_reset 12.000s 4742.994us 1 1 100.00
aes_core_fi 10.000s 552.741us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 4.000s 115.815us 1 1 100.00
aes_config_error 3.000s 87.728us 1 1 100.00
aes_stress 5.000s 252.501us 1 1 100.00
aes_core_fi 10.000s 552.741us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 183.550us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 57.352us 1 1 100.00
aes_stress 5.000s 252.501us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 5.000s 252.501us 1 1 100.00
aes_sideload 4.000s 99.624us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 57.352us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 57.352us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 57.352us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 57.352us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 57.352us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 5.000s 252.501us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 5.000s 252.501us 1 1 100.00
sec_cm_main_fsm_sparse 1 1 100.00
aes_fi 2.000s 114.635us 1 1 100.00
sec_cm_main_fsm_redun 4 4 100.00
aes_fi 2.000s 114.635us 1 1 100.00
aes_control_fi 2.000s 50.917us 1 1 100.00
aes_cipher_fi 2.000s 46.979us 1 1 100.00
aes_ctr_fi 3.000s 65.979us 1 1 100.00
sec_cm_cipher_fsm_sparse 1 1 100.00
aes_fi 2.000s 114.635us 1 1 100.00
sec_cm_cipher_fsm_redun 3 3 100.00
aes_fi 2.000s 114.635us 1 1 100.00
aes_control_fi 2.000s 50.917us 1 1 100.00
aes_cipher_fi 2.000s 46.979us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 46.979us 1 1 100.00
sec_cm_ctr_fsm_sparse 1 1 100.00
aes_fi 2.000s 114.635us 1 1 100.00
sec_cm_ctr_fsm_redun 3 3 100.00
aes_fi 2.000s 114.635us 1 1 100.00
aes_control_fi 2.000s 50.917us 1 1 100.00
aes_ctr_fi 3.000s 65.979us 1 1 100.00
sec_cm_ghash_fsm_sparse 1 1 100.00
aes_fi 2.000s 114.635us 1 1 100.00
sec_cm_ctrl_sparse 4 4 100.00
aes_fi 2.000s 114.635us 1 1 100.00
aes_control_fi 2.000s 50.917us 1 1 100.00
aes_cipher_fi 2.000s 46.979us 1 1 100.00
aes_ctr_fi 3.000s 65.979us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 12.000s 4742.994us 1 1 100.00
sec_cm_main_fsm_local_esc 4 4 100.00
aes_fi 2.000s 114.635us 1 1 100.00
aes_control_fi 2.000s 50.917us 1 1 100.00
aes_cipher_fi 2.000s 46.979us 1 1 100.00
aes_ctr_fi 3.000s 65.979us 1 1 100.00
sec_cm_cipher_fsm_local_esc 4 4 100.00
aes_fi 2.000s 114.635us 1 1 100.00
aes_control_fi 2.000s 50.917us 1 1 100.00
aes_cipher_fi 2.000s 46.979us 1 1 100.00
aes_ctr_fi 3.000s 65.979us 1 1 100.00
sec_cm_ctr_fsm_local_esc 3 3 100.00
aes_fi 2.000s 114.635us 1 1 100.00
aes_control_fi 2.000s 50.917us 1 1 100.00
aes_ctr_fi 3.000s 65.979us 1 1 100.00
sec_cm_ghash_fsm_local_esc 2 2 100.00
aes_fi 2.000s 114.635us 1 1 100.00
aes_ghash_fi 3.000s 146.527us 1 1 100.00
sec_cm_data_reg_local_esc 3 3 100.00
aes_fi 2.000s 114.635us 1 1 100.00
aes_control_fi 2.000s 50.917us 1 1 100.00
aes_cipher_fi 2.000s 46.979us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 9.000s 70.383us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_base_vseq.sv:75) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed)
aes_stress_all_with_rand_reset 69384105897018689621580702621089859047009322798205192668447459250621931890562 188
UVM_INFO @ 70382915 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---