Simulation Results: aes/unmasked

 
21/04/2026 00:01:59 DVSim: v1.32.0 sha: 089baca json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 86.06 %
  • code
  • 91.60 %
  • assert
  • 97.75 %
  • func
  • 68.83 %
  • block
  • 91.31 %
  • line
  • 93.52 %
  • branch
  • 84.12 %
  • toggle
  • 97.99 %
  • FSM
  • 90.78 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 2.000s 62.940us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 68.723us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 1.000s 65.610us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 74.064us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 4.000s 290.969us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 323.095us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 273.145us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 74.064us 1 1 100.00
aes_csr_aliasing 2.000s 323.095us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 68.723us 1 1 100.00
aes_config_error 2.000s 116.000us 1 1 100.00
aes_stress 3.000s 68.577us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 68.723us 1 1 100.00
aes_config_error 2.000s 116.000us 1 1 100.00
aes_stress 3.000s 68.577us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 68.577us 1 1 100.00
aes_b2b 2.000s 80.035us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 68.577us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 68.723us 1 1 100.00
aes_config_error 2.000s 116.000us 1 1 100.00
aes_stress 3.000s 68.577us 1 1 100.00
aes_alert_reset 2.000s 101.231us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 3.000s 141.153us 1 1 100.00
aes_config_error 2.000s 116.000us 1 1 100.00
aes_alert_reset 2.000s 101.231us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 95.186us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 4.000s 1287.582us 1 1 100.00
nist_test_vectors_gcm 1 1 100.00
aes_nist_vectors_gcm 5.000s 1272.252us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 2.000s 101.231us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 68.577us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 68.577us 1 1 100.00
aes_sideload 3.000s 422.611us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 145.265us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 10.000s 329.728us 1 1 100.00
gcm_save_and_restore 1 1 100.00
aes_gcm_save_restore 3.000s 191.834us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 63.911us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 2.000s 197.138us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 2.000s 197.138us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 1.000s 65.610us 1 1 100.00
aes_csr_rw 2.000s 74.064us 1 1 100.00
aes_csr_aliasing 2.000s 323.095us 1 1 100.00
aes_same_csr_outstanding 2.000s 74.331us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 1.000s 65.610us 1 1 100.00
aes_csr_rw 2.000s 74.064us 1 1 100.00
aes_csr_aliasing 2.000s 323.095us 1 1 100.00
aes_same_csr_outstanding 2.000s 74.331us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 3.000s 121.684us 1 1 100.00
fault_inject 3 3 100.00
aes_fi 3.000s 179.947us 1 1 100.00
aes_control_fi 1.000s 151.150us 1 1 100.00
aes_cipher_fi 1.000s 62.313us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 1.000s 165.277us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 1.000s 165.277us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 1.000s 165.277us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 1.000s 165.277us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 307.612us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 2.000s 1080.159us 1 1 100.00
aes_tl_intg_err 2.000s 154.989us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 154.989us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 2.000s 101.231us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 165.277us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 165.277us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 68.723us 1 1 100.00
aes_stress 3.000s 68.577us 1 1 100.00
aes_alert_reset 2.000s 101.231us 1 1 100.00
aes_core_fi 2.000s 92.942us 1 1 100.00
sec_cm_gcm_config_sparse 4 4 100.00
aes_gcm_save_restore 3.000s 191.834us 1 1 100.00
aes_config_error 2.000s 116.000us 1 1 100.00
aes_stress 3.000s 68.577us 1 1 100.00
aes_core_fi 2.000s 92.942us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 165.277us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 96.561us 1 1 100.00
aes_stress 3.000s 68.577us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 68.577us 1 1 100.00
aes_sideload 3.000s 422.611us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 96.561us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 96.561us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 96.561us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 96.561us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 96.561us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 68.577us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 68.577us 1 1 100.00
sec_cm_main_fsm_sparse 1 1 100.00
aes_fi 3.000s 179.947us 1 1 100.00
sec_cm_main_fsm_redun 4 4 100.00
aes_fi 3.000s 179.947us 1 1 100.00
aes_control_fi 1.000s 151.150us 1 1 100.00
aes_cipher_fi 1.000s 62.313us 1 1 100.00
aes_ctr_fi 2.000s 94.225us 1 1 100.00
sec_cm_cipher_fsm_sparse 1 1 100.00
aes_fi 3.000s 179.947us 1 1 100.00
sec_cm_cipher_fsm_redun 3 3 100.00
aes_fi 3.000s 179.947us 1 1 100.00
aes_control_fi 1.000s 151.150us 1 1 100.00
aes_cipher_fi 1.000s 62.313us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 1.000s 62.313us 1 1 100.00
sec_cm_ctr_fsm_sparse 1 1 100.00
aes_fi 3.000s 179.947us 1 1 100.00
sec_cm_ctr_fsm_redun 3 3 100.00
aes_fi 3.000s 179.947us 1 1 100.00
aes_control_fi 1.000s 151.150us 1 1 100.00
aes_ctr_fi 2.000s 94.225us 1 1 100.00
sec_cm_ghash_fsm_sparse 1 1 100.00
aes_fi 3.000s 179.947us 1 1 100.00
sec_cm_ctrl_sparse 4 4 100.00
aes_fi 3.000s 179.947us 1 1 100.00
aes_control_fi 1.000s 151.150us 1 1 100.00
aes_cipher_fi 1.000s 62.313us 1 1 100.00
aes_ctr_fi 2.000s 94.225us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 2.000s 101.231us 1 1 100.00
sec_cm_main_fsm_local_esc 4 4 100.00
aes_fi 3.000s 179.947us 1 1 100.00
aes_control_fi 1.000s 151.150us 1 1 100.00
aes_cipher_fi 1.000s 62.313us 1 1 100.00
aes_ctr_fi 2.000s 94.225us 1 1 100.00
sec_cm_cipher_fsm_local_esc 4 4 100.00
aes_fi 3.000s 179.947us 1 1 100.00
aes_control_fi 1.000s 151.150us 1 1 100.00
aes_cipher_fi 1.000s 62.313us 1 1 100.00
aes_ctr_fi 2.000s 94.225us 1 1 100.00
sec_cm_ctr_fsm_local_esc 3 3 100.00
aes_fi 3.000s 179.947us 1 1 100.00
aes_control_fi 1.000s 151.150us 1 1 100.00
aes_ctr_fi 2.000s 94.225us 1 1 100.00
sec_cm_ghash_fsm_local_esc 2 2 100.00
aes_fi 3.000s 179.947us 1 1 100.00
aes_ghash_fi 2.000s 66.308us 1 1 100.00
sec_cm_data_reg_local_esc 3 3 100.00
aes_fi 3.000s 179.947us 1 1 100.00
aes_control_fi 1.000s 151.150us 1 1 100.00
aes_cipher_fi 1.000s 62.313us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 10.000s 424.278us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_base_vseq.sv:75) [aes_stress_vseq] Check failed (aes_ctrl_aux[*] == cfg.do_reseed)
aes_stress_all_with_rand_reset 91854789404923686798202260485152931826213196708607478920689488803173702599448 349
UVM_INFO @ 424278100 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---