Simulation Results: alert_handler

 
21/04/2026 00:01:59 DVSim: v1.32.0 sha: 089baca json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.73 %
  • code
  • 93.83 %
  • assert
  • 98.33 %
  • func
  • 80.02 %
  • line
  • 99.77 %
  • branch
  • 98.19 %
  • cond
  • 91.67 %
  • toggle
  • 94.02 %
  • FSM
  • 85.48 %
Validation stages
V1
100.00%
V2
94.74%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 13.590s 337.608us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 2.820s 43.794us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 3.090s 186.642us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 165.370s 8755.718us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 70.120s 3330.744us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 5.310s 101.572us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 3.090s 186.642us 1 1 100.00
alert_handler_csr_aliasing 70.120s 3330.744us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 64.050s 5114.000us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 5.380s 336.180us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 399.430s 5423.869us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 32.330s 3330.063us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 13.590s 337.608us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 31.860s 830.086us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 27.780s 2454.271us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 197.650s 27995.706us 0 1 0.00
lpg 2 2 100.00
alert_handler_lpg 713.660s 52959.562us 1 1 100.00
alert_handler_lpg_stub_clk 1295.030s 169053.729us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 693.330s 42287.154us 1 1 100.00
alert_handler_entropy_stress_test 1 1 100.00
alert_handler_entropy_stress 5.210s 130.546us 1 1 100.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 2.140s 29.970us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.340s 11.886us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 4.760s 61.123us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 4.760s 61.123us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 2.820s 43.794us 1 1 100.00
alert_handler_csr_rw 3.090s 186.642us 1 1 100.00
alert_handler_csr_aliasing 70.120s 3330.744us 1 1 100.00
alert_handler_same_csr_outstanding 15.380s 1394.427us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 2.820s 43.794us 1 1 100.00
alert_handler_csr_rw 3.090s 186.642us 1 1 100.00
alert_handler_csr_aliasing 70.120s 3330.744us 1 1 100.00
alert_handler_same_csr_outstanding 15.380s 1394.427us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 89.290s 7346.264us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 89.290s 7346.264us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 89.290s 7346.264us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 89.290s 7346.264us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 368.200s 9559.310us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 8.930s 241.051us 1 1 100.00
alert_handler_tl_intg_err 52.010s 4954.015us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 52.010s 4954.015us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 89.290s 7346.264us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 13.590s 337.608us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 13.590s 337.608us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 13.590s 337.608us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 13.590s 337.608us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 32.330s 3330.063us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 713.660s 52959.562us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 32.330s 3330.063us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 399.430s 5423.869us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 399.430s 5423.869us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 8.930s 241.051us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 8.930s 241.051us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 8.930s 241.051us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 8.930s 241.051us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 8.930s 241.051us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 8.930s 241.051us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 8.930s 241.051us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 8.930s 241.051us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 8.930s 241.051us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
alert_handler_stress_all_with_rand_reset 274.330s 3807.355us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state
alert_handler_ping_timeout 99767288949424068844301274548481404930760697225294560260919932959404463771586 135
UVM_INFO @ 27995706266 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---