Simulation Results

Simulation Results: chip

21/04/2026 00:01:59 DVSim: v1.32.0 sha: 089baca json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
74.48 %

code
85.06 %

assert
97.37 %

func
41.01 %

line
94.17 %

branch
93.54 %

cond
89.16 %

toggle
91.30 %

FSM
57.14 %

Validation stages

V1		100.00%
V2		77.70%
V2S		50.00%
V3		65.38%
unmapped		70.00%

18/18 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_example_tests				4	4	100.00
	chip_sw_example_flash	165.920s	2759.744us	1	1	100.00
	chip_sw_example_rom	69.380s	2781.569us	1	1	100.00
	chip_sw_example_manufacturer	154.740s	3125.667us	1	1	100.00
	chip_sw_example_concurrency	173.360s	3221.397us	1	1	100.00
csr_hw_reset				1	1	100.00
	chip_csr_hw_reset	319.180s	6857.545us	1	1	100.00
csr_rw				1	1	100.00
	chip_csr_rw	202.820s	3893.369us	1	1	100.00
csr_bit_bash				1	1	100.00
	chip_csr_bit_bash	367.510s	5686.670us	1	1	100.00
csr_aliasing				1	1	100.00
	chip_csr_aliasing	3383.240s	28754.491us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	chip_csr_mem_rw_with_rand_reset	676.820s	10302.856us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	chip_csr_aliasing	3383.240s	28754.491us	1	1	100.00
	chip_csr_rw	202.820s	3893.369us	1	1	100.00
xbar_smoke				1	1	100.00
	xbar_smoke	4.710s	41.360us	1	1	100.00
chip_sw_gpio_out				1	1	100.00
	chip_sw_gpio	271.250s	4560.108us	1	1	100.00
chip_sw_gpio_in				1	1	100.00
	chip_sw_gpio	271.250s	4560.108us	1	1	100.00
chip_sw_gpio_irq				1	1	100.00
	chip_sw_gpio	271.250s	4560.108us	1	1	100.00
chip_sw_uart_tx_rx				1	1	100.00
	chip_sw_uart_tx_rx	417.820s	5055.369us	1	1	100.00
chip_sw_uart_rx_overflow				4	4	100.00
	chip_sw_uart_tx_rx	417.820s	5055.369us	1	1	100.00
	chip_sw_uart_tx_rx_idx1	397.350s	4768.568us	1	1	100.00
	chip_sw_uart_tx_rx_idx2	302.120s	4026.630us	1	1	100.00
	chip_sw_uart_tx_rx_idx3	336.440s	4637.597us	1	1	100.00
chip_sw_uart_baud_rate				1	1	100.00
	chip_sw_uart_rand_baudrate	324.490s	4819.438us	1	1	100.00
chip_sw_uart_tx_rx_alt_clk_freq				2	2	100.00
	chip_sw_uart_tx_rx_alt_clk_freq	1099.770s	9310.446us	1	1	100.00
	chip_sw_uart_tx_rx_alt_clk_freq_low_speed	271.430s	4207.878us	1	1	100.00

216/278 passed

77.70 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_pin_mux				1	1	100.00
	chip_padctrl_attributes	193.520s	4550.832us	1	1	100.00
chip_padctrl_attributes				1	1	100.00
	chip_padctrl_attributes	193.520s	4550.832us	1	1	100.00
chip_sw_sleep_pin_mio_dio_val				1	1	100.00
	chip_sw_sleep_pin_mio_dio_val	146.170s	2749.377us	1	1	100.00
chip_sw_sleep_pin_wake				1	1	100.00
	chip_sw_sleep_pin_wake	145.960s	3046.446us	1	1	100.00
chip_sw_sleep_pin_retention				1	1	100.00
	chip_sw_sleep_pin_retention	203.180s	4708.799us	1	1	100.00
chip_sw_tap_strap_sampling				4	4	100.00
	chip_tap_straps_dev	509.890s	8237.686us	1	1	100.00
	chip_tap_straps_testunlock0	317.190s	6308.375us	1	1	100.00
	chip_tap_straps_rma	251.220s	4810.379us	1	1	100.00
	chip_tap_straps_prod	86.480s	3114.764us	1	1	100.00
chip_sw_pattgen_ios				1	1	100.00
	chip_sw_pattgen_ios	137.060s	2571.829us	1	1	100.00
chip_sw_sleep_pwm_pulses				1	1	100.00
	chip_sw_sleep_pwm_pulses	736.520s	8785.900us	1	1	100.00
chip_sw_data_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	357.180s	5081.860us	1	1	100.00
chip_sw_instruction_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	357.180s	5081.860us	1	1	100.00
chip_sw_ast_clk_outputs				1	1	100.00
	chip_sw_ast_clk_outputs	630.310s	8208.303us	1	1	100.00
chip_sw_ast_clk_rst_inputs				0	1	0.00
	chip_sw_ast_clk_rst_inputs	1166.980s	10813.441us	0	1	0.00
chip_sw_ast_sys_clk_jitter				10	10	100.00
	chip_sw_flash_ctrl_ops_jitter_en	366.270s	4736.318us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	632.420s	6318.838us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3824.590s	20382.493us	1	1	100.00
	chip_sw_aes_enc_jitter_en	194.460s	3652.578us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	776.910s	7825.790us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	184.240s	3672.551us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	1357.420s	10409.437us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	179.050s	2912.725us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	268.060s	3951.135us	1	1	100.00
	chip_sw_clkmgr_jitter	154.250s	2854.021us	1	1	100.00
chip_sw_ast_usb_clk_calib				1	1	100.00
	chip_sw_usb_ast_clk_calib	199.040s	2762.582us	1	1	100.00
chip_sw_sensor_ctrl_ast_alerts				2	2	100.00
	chip_sw_sensor_ctrl_alert	556.710s	6844.139us	1	1	100.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	228.790s	5099.801us	1	1	100.00
chip_sw_sensor_ctrl_ast_status				1	1	100.00
	chip_sw_sensor_ctrl_status	120.150s	2632.616us	1	1	100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup				1	1	100.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	228.790s	5099.801us	1	1	100.00
chip_sw_smoketest				17	17	100.00
	chip_sw_flash_scrambling_smoketest	181.360s	2810.108us	1	1	100.00
	chip_sw_aes_smoketest	214.940s	3284.290us	1	1	100.00
	chip_sw_aon_timer_smoketest	211.500s	2883.943us	1	1	100.00
	chip_sw_clkmgr_smoketest	150.280s	2316.618us	1	1	100.00
	chip_sw_csrng_smoketest	145.520s	2832.377us	1	1	100.00
	chip_sw_entropy_src_smoketest	901.110s	6636.503us	1	1	100.00
	chip_sw_gpio_smoketest	202.320s	2836.164us	1	1	100.00
	chip_sw_hmac_smoketest	179.050s	3307.800us	1	1	100.00
	chip_sw_kmac_smoketest	154.060s	3168.675us	1	1	100.00
	chip_sw_otbn_smoketest	908.340s	7683.850us	1	1	100.00
	chip_sw_pwrmgr_smoketest	245.470s	5313.456us	1	1	100.00
	chip_sw_pwrmgr_usbdev_smoketest	247.450s	6391.947us	1	1	100.00
	chip_sw_rv_plic_smoketest	172.120s	3081.928us	1	1	100.00
	chip_sw_rv_timer_smoketest	156.920s	2653.555us	1	1	100.00
	chip_sw_rstmgr_smoketest	173.390s	3592.866us	1	1	100.00
	chip_sw_sram_ctrl_smoketest	159.070s	3531.526us	1	1	100.00
	chip_sw_uart_smoketest	169.700s	3161.527us	1	1	100.00
chip_sw_otp_smoketest				1	1	100.00
	chip_sw_otp_ctrl_smoketest	182.250s	3058.384us	1	1	100.00
chip_sw_rom_functests				0	1	0.00
	rom_keymgr_functest	373.410s	4537.875us	0	1	0.00
chip_sw_boot				1	1	100.00
	chip_sw_uart_tx_rx_bootstrap	7849.940s	63322.472us	1	1	100.00
chip_sw_secure_boot				1	1	100.00
	rom_e2e_smoke	2966.160s	15756.197us	1	1	100.00
chip_sw_rom_raw_unlock				0	1	0.00
	rom_raw_unlock	127.974s	0.000us	0	1	0.00
chip_sw_power_idle_load				0	1	0.00
	chip_sw_power_idle_load	210.650s	3105.253us	0	1	0.00
chip_sw_power_sleep_load				0	1	0.00
	chip_sw_power_sleep_load	171.170s	3795.715us	0	1	0.00
chip_sw_exit_test_unlocked_bootstrap				1	1	100.00
	chip_sw_exit_test_unlocked_bootstrap	7355.260s	56281.235us	1	1	100.00
chip_sw_inject_scramble_seed				1	1	100.00
	chip_sw_inject_scramble_seed	7645.850s	57602.344us	1	1	100.00
tl_d_oob_addr_access				0	1	0.00
	chip_tl_errors	56.330s	2777.293us	0	1	0.00
tl_d_illegal_access				0	1	0.00
	chip_tl_errors	56.330s	2777.293us	0	1	0.00
tl_d_outstanding_access				4	4	100.00
	chip_csr_aliasing	3383.240s	28754.491us	1	1	100.00
	chip_same_csr_outstanding	2917.590s	32334.913us	1	1	100.00
	chip_csr_hw_reset	319.180s	6857.545us	1	1	100.00
	chip_csr_rw	202.820s	3893.369us	1	1	100.00
tl_d_partial_access				4	4	100.00
	chip_csr_aliasing	3383.240s	28754.491us	1	1	100.00
	chip_same_csr_outstanding	2917.590s	32334.913us	1	1	100.00
	chip_csr_hw_reset	319.180s	6857.545us	1	1	100.00
	chip_csr_rw	202.820s	3893.369us	1	1	100.00
xbar_base_random_sequence				1	1	100.00
	xbar_random	12.370s	442.349us	1	1	100.00
xbar_random_delay				6	6	100.00
	xbar_smoke_zero_delays	5.090s	52.607us	1	1	100.00
	xbar_smoke_large_delays	43.400s	6326.587us	1	1	100.00
	xbar_smoke_slow_rsp	40.940s	4282.466us	1	1	100.00
	xbar_random_zero_delays	29.150s	489.276us	1	1	100.00
	xbar_random_large_delays	237.860s	35908.669us	1	1	100.00
	xbar_random_slow_rsp	164.680s	17904.412us	1	1	100.00
xbar_unmapped_address				2	2	100.00
	xbar_unmapped_addr	37.240s	1049.110us	1	1	100.00
	xbar_error_and_unmapped_addr	12.790s	157.608us	1	1	100.00
xbar_error_cases				2	2	100.00
	xbar_error_random	43.740s	2063.727us	1	1	100.00
	xbar_error_and_unmapped_addr	12.790s	157.608us	1	1	100.00
xbar_all_access_same_device				2	2	100.00
	xbar_access_same_device	49.080s	1139.513us	1	1	100.00
	xbar_access_same_device_slow_rsp	410.670s	47024.765us	1	1	100.00
xbar_all_hosts_use_same_source_id				1	1	100.00
	xbar_same_source	13.670s	246.608us	1	1	100.00
xbar_stress_all				2	2	100.00
	xbar_stress_all	160.670s	3119.864us	1	1	100.00
	xbar_stress_all_with_error	277.190s	12951.723us	1	1	100.00
xbar_stress_with_reset				2	2	100.00
	xbar_stress_all_with_rand_reset	104.770s	410.053us	1	1	100.00
	xbar_stress_all_with_reset_error	336.810s	11253.798us	1	1	100.00
rom_e2e_smoke				1	1	100.00
	rom_e2e_smoke	2966.160s	15756.197us	1	1	100.00
rom_e2e_shutdown_output				1	1	100.00
	rom_e2e_shutdown_output	2455.040s	30405.995us	1	1	100.00
rom_e2e_shutdown_exception_c				1	1	100.00
	rom_e2e_shutdown_exception_c	3002.750s	15227.743us	1	1	100.00
rom_e2e_boot_policy_valid				0	15	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	155.451s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_dev	21.498s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod	26.589s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod_end	18.502s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_rma	23.065s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	139.078s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_dev	7.567s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod	86.353s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	21.457s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_rma	11.460s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	165.347s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_dev	45.081s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod	9.974s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	11.515s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_rma	10.944s	0.000us	0	1	0.00
rom_e2e_sigverify_always				0	15	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	17.250s	10.160us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_dev	17.230s	10.120us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod	17.680s	10.400us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod_end	20.770s	10.320us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_rma	20.150s	10.100us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	16.740s	10.380us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_dev	17.270s	10.320us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod	20.390s	10.340us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	17.060s	10.120us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_rma	17.300s	10.200us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	16.860s	10.300us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_dev	17.180s	10.400us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod	16.620s	10.140us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	21.120s	10.280us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_rma	19.280s	10.220us	0	1	0.00
rom_e2e_asm_init				0	5	0.00
	rom_e2e_asm_init_test_unlocked0	148.194s	0.000us	0	1	0.00
	rom_e2e_asm_init_dev	63.191s	0.000us	0	1	0.00
	rom_e2e_asm_init_prod	51.563s	0.000us	0	1	0.00
	rom_e2e_asm_init_prod_end	66.887s	0.000us	0	1	0.00
	rom_e2e_asm_init_rma	37.782s	0.000us	0	1	0.00
rom_e2e_keymgr_init				2	3	66.67
	rom_e2e_keymgr_init_rom_ext_meas	3120.510s	19439.680us	0	1	0.00
	rom_e2e_keymgr_init_rom_ext_no_meas	5813.380s	29535.992us	1	1	100.00
	rom_e2e_keymgr_init_rom_ext_invalid_meas	5732.490s	29141.604us	1	1	100.00
rom_e2e_static_critical				1	1	100.00
	rom_e2e_static_critical	3201.720s	16117.694us	1	1	100.00
chip_sw_adc_ctrl_debug_cable_irq				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3136.370s	34777.099us	0	1	0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3136.370s	34777.099us	0	1	0.00
chip_sw_aes_enc				2	2	100.00
	chip_sw_aes_enc	192.350s	3152.601us	1	1	100.00
	chip_sw_aes_enc_jitter_en	194.460s	3652.578us	1	1	100.00
chip_sw_aes_entropy				1	1	100.00
	chip_sw_aes_entropy	138.440s	2427.004us	1	1	100.00
chip_sw_aes_idle				1	1	100.00
	chip_sw_aes_idle	159.120s	2701.821us	1	1	100.00
chip_sw_aes_sideload				1	1	100.00
	chip_sw_keymgr_sideload_aes	691.340s	7817.862us	1	1	100.00
chip_sw_alert_handler_alerts				0	1	0.00
	chip_sw_alert_test	193.730s	3401.610us	0	1	0.00
chip_sw_alert_handler_escalations				1	1	100.00
	chip_sw_alert_handler_escalation	347.430s	4872.644us	1	1	100.00
chip_sw_all_escalation_resets				1	1	100.00
	chip_sw_all_escalation_resets	450.390s	5935.146us	1	1	100.00
chip_sw_alert_handler_irqs				3	3	100.00
	chip_plic_all_irqs_0	501.460s	5510.789us	1	1	100.00
	chip_plic_all_irqs_10	263.370s	3381.745us	1	1	100.00
	chip_plic_all_irqs_20	352.290s	4820.076us	1	1	100.00
chip_sw_alert_handler_entropy				1	1	100.00
	chip_sw_alert_handler_entropy	209.360s	3583.806us	1	1	100.00
chip_sw_alert_handler_crashdump				1	1	100.00
	chip_sw_rstmgr_alert_info	1072.680s	13736.122us	1	1	100.00
chip_sw_alert_handler_ping_timeout				1	1	100.00
	chip_sw_alert_handler_ping_timeout	207.250s	3679.817us	1	1	100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_alerts	146.160s	2660.088us	0	1	0.00
chip_sw_alert_handler_lpg_sleep_mode_pings				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_pings	0.000s	0.000us	0	1	0.00
chip_sw_alert_handler_lpg_clock_off				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	808.240s	6245.608us	1	1	100.00
chip_sw_alert_handler_lpg_reset_toggle				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	720.240s	6103.315us	1	1	100.00
chip_sw_alert_handler_ping_ok				1	1	100.00
	chip_sw_alert_handler_ping_ok	848.360s	8419.648us	1	1	100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep				1	1	100.00
	chip_sw_alert_handler_reverse_ping_in_deep_sleep	8729.480s	254781.432us	1	1	100.00
chip_sw_aon_timer_wakeup_irq				1	1	100.00
	chip_sw_aon_timer_irq	223.590s	3395.110us	1	1	100.00
chip_sw_aon_timer_sleep_wakeup				1	1	100.00
	chip_sw_pwrmgr_smoketest	245.470s	5313.456us	1	1	100.00
chip_sw_aon_timer_wdog_bark_irq				1	1	100.00
	chip_sw_aon_timer_irq	223.590s	3395.110us	1	1	100.00
chip_sw_aon_timer_wdog_bite_reset				0	1	0.00
	chip_sw_aon_timer_wdog_bite_reset	422.820s	8731.740us	0	1	0.00
chip_sw_aon_timer_sleep_wdog_bite_reset				0	1	0.00
	chip_sw_aon_timer_wdog_bite_reset	422.820s	8731.740us	0	1	0.00
chip_sw_aon_timer_sleep_wdog_sleep_pause				1	1	100.00
	chip_sw_aon_timer_sleep_wdog_sleep_pause	368.650s	7519.964us	1	1	100.00
chip_sw_aon_timer_wdog_lc_escalate				1	1	100.00
	chip_sw_aon_timer_wdog_lc_escalate	412.500s	5289.167us	1	1	100.00
chip_sw_clkmgr_idle_trans				4	4	100.00
	chip_sw_otbn_randomness	546.750s	6657.076us	1	1	100.00
	chip_sw_aes_idle	159.120s	2701.821us	1	1	100.00
	chip_sw_hmac_enc_idle	178.030s	3140.449us	1	1	100.00
	chip_sw_kmac_idle	170.860s	3391.437us	1	1	100.00
chip_sw_clkmgr_off_trans				4	4	100.00
	chip_sw_clkmgr_off_aes_trans	373.890s	5651.273us	1	1	100.00
	chip_sw_clkmgr_off_hmac_trans	313.230s	4958.859us	1	1	100.00
	chip_sw_clkmgr_off_kmac_trans	280.600s	4382.527us	1	1	100.00
	chip_sw_clkmgr_off_otbn_trans	274.780s	4376.550us	1	1	100.00
chip_sw_clkmgr_off_peri				1	1	100.00
	chip_sw_clkmgr_off_peri	731.390s	11268.254us	1	1	100.00
chip_sw_clkmgr_div				7	7	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	362.390s	4106.376us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	345.310s	4125.805us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	406.820s	3939.254us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	380.230s	5176.989us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	405.120s	4270.261us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	395.360s	5154.683us	1	1	100.00
	chip_sw_ast_clk_outputs	630.310s	8208.303us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_lc				1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	330.290s	6988.777us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_sw				2	2	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	406.820s	3939.254us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	380.230s	5176.989us	1	1	100.00
chip_sw_clkmgr_jitter				10	10	100.00
	chip_sw_flash_ctrl_ops_jitter_en	366.270s	4736.318us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	632.420s	6318.838us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3824.590s	20382.493us	1	1	100.00
	chip_sw_aes_enc_jitter_en	194.460s	3652.578us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	776.910s	7825.790us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	184.240s	3672.551us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	1357.420s	10409.437us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	179.050s	2912.725us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	268.060s	3951.135us	1	1	100.00
	chip_sw_clkmgr_jitter	154.250s	2854.021us	1	1	100.00
chip_sw_clkmgr_extended_range				11	11	100.00
	chip_sw_clkmgr_jitter_reduced_freq	143.410s	3210.554us	1	1	100.00
	chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	385.150s	4929.276us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en_reduced_freq	679.320s	6845.021us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	3705.000s	25343.982us	1	1	100.00
	chip_sw_aes_enc_jitter_en_reduced_freq	140.860s	2929.915us	1	1	100.00
	chip_sw_hmac_enc_jitter_en_reduced_freq	146.440s	2680.871us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	1137.500s	11176.951us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	179.100s	2583.154us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	327.550s	5135.911us	1	1	100.00
	chip_sw_flash_init_reduced_freq	1351.140s	24553.402us	1	1	100.00
	chip_sw_csrng_edn_concurrency_reduced_freq	2278.320s	18163.256us	1	1	100.00
chip_sw_clkmgr_deep_sleep_frequency				1	1	100.00
	chip_sw_ast_clk_outputs	630.310s	8208.303us	1	1	100.00
chip_sw_clkmgr_sleep_frequency				1	1	100.00
	chip_sw_clkmgr_sleep_frequency	395.450s	5524.788us	1	1	100.00
chip_sw_clkmgr_reset_frequency				1	1	100.00
	chip_sw_clkmgr_reset_frequency	253.150s	2878.733us	1	1	100.00
chip_sw_clkmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	450.390s	5935.146us	1	1	100.00
chip_sw_clkmgr_alert_handler_clock_enables				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	808.240s	6245.608us	1	1	100.00
chip_sw_csrng_edn_cmd				1	1	100.00
	chip_sw_entropy_src_csrng	887.530s	6574.249us	1	1	100.00
chip_sw_csrng_fuse_en_sw_app_read				0	1	0.00
	chip_sw_csrng_fuse_en_sw_app_read_test	145.070s	3084.965us	0	1	0.00
chip_sw_csrng_lc_hw_debug_en				1	1	100.00
	chip_sw_csrng_lc_hw_debug_en_test	468.330s	7677.530us	1	1	100.00
chip_sw_csrng_known_answer_tests				1	1	100.00
	chip_sw_csrng_kat_test	208.670s	3031.929us	1	1	100.00
chip_sw_edn_entropy_reqs				3	3	100.00
	chip_sw_csrng_edn_concurrency	2072.440s	12559.586us	1	1	100.00
	chip_sw_entropy_src_ast_rng_req	186.620s	3552.616us	1	1	100.00
	chip_sw_edn_entropy_reqs	830.900s	6966.231us	1	1	100.00
chip_sw_entropy_src_ast_rng_req				1	1	100.00
	chip_sw_entropy_src_ast_rng_req	186.620s	3552.616us	1	1	100.00
chip_sw_entropy_src_csrng				1	1	100.00
	chip_sw_entropy_src_csrng	887.530s	6574.249us	1	1	100.00
chip_sw_entropy_src_known_answer_tests				1	1	100.00
	chip_sw_entropy_src_kat_test	128.270s	2829.449us	1	1	100.00
chip_sw_flash_init				1	1	100.00
	chip_sw_flash_init	1117.370s	22194.164us	1	1	100.00
chip_sw_flash_host_access				2	2	100.00
	chip_sw_flash_ctrl_access	574.850s	5341.670us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	632.420s	6318.838us	1	1	100.00
chip_sw_flash_ctrl_ops				2	2	100.00
	chip_sw_flash_ctrl_ops	336.110s	4604.714us	1	1	100.00
	chip_sw_flash_ctrl_ops_jitter_en	366.270s	4736.318us	1	1	100.00
chip_sw_flash_rma_unlocked				1	1	100.00
	chip_sw_flash_rma_unlocked	3838.720s	43854.948us	1	1	100.00
chip_sw_flash_scramble				1	1	100.00
	chip_sw_flash_init	1117.370s	22194.164us	1	1	100.00
chip_sw_flash_idle_low_power				1	1	100.00
	chip_sw_flash_ctrl_idle_low_power	209.970s	3738.067us	1	1	100.00
chip_sw_flash_keymgr_seeds				1	1	100.00
	chip_sw_keymgr_key_derivation	1579.340s	11814.903us	1	1	100.00
chip_sw_flash_lc_creator_seed_sw_rw_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	116.250s	2528.788us	0	1	0.00
chip_sw_flash_creator_seed_wipe_on_rma				1	1	100.00
	chip_sw_flash_rma_unlocked	3838.720s	43854.948us	1	1	100.00
chip_sw_flash_lc_owner_seed_sw_rw_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	116.250s	2528.788us	0	1	0.00
chip_sw_flash_lc_iso_part_sw_rd_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	116.250s	2528.788us	0	1	0.00
chip_sw_flash_lc_iso_part_sw_wr_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	116.250s	2528.788us	0	1	0.00
chip_sw_flash_lc_seed_hw_rd_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	116.250s	2528.788us	0	1	0.00
chip_sw_flash_lc_escalate_en				1	1	100.00
	chip_sw_all_escalation_resets	450.390s	5935.146us	1	1	100.00
chip_sw_flash_prim_tl_access				1	1	100.00
	chip_prim_tl_access	178.170s	5899.388us	1	1	100.00
chip_sw_flash_ctrl_clock_freqs				1	1	100.00
	chip_sw_flash_ctrl_clock_freqs	521.050s	5505.145us	1	1	100.00
chip_sw_flash_ctrl_escalation_reset				1	1	100.00
	chip_sw_flash_crash_alert	353.890s	4536.303us	1	1	100.00
chip_sw_flash_ctrl_write_clear				1	1	100.00
	chip_sw_flash_crash_alert	353.890s	4536.303us	1	1	100.00
chip_sw_hmac_enc				2	2	100.00
	chip_sw_hmac_enc	145.560s	2916.639us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	184.240s	3672.551us	1	1	100.00
chip_sw_hmac_idle				1	1	100.00
	chip_sw_hmac_enc_idle	178.030s	3140.449us	1	1	100.00
chip_sw_hmac_all_configurations				1	1	100.00
	chip_sw_hmac_oneshot	690.400s	5190.588us	1	1	100.00
chip_sw_hmac_multistream_mode				1	1	100.00
	chip_sw_hmac_multistream	692.360s	5941.206us	1	1	100.00
chip_sw_i2c_host_tx_rx				3	3	100.00
	chip_sw_i2c_host_tx_rx	394.340s	4733.284us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx1	428.420s	5816.630us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx2	498.890s	5752.744us	1	1	100.00
chip_sw_i2c_device_tx_rx				1	1	100.00
	chip_sw_i2c_device_tx_rx	326.780s	4392.011us	1	1	100.00
chip_sw_keymgr_key_derivation				2	2	100.00
	chip_sw_keymgr_key_derivation	1579.340s	11814.903us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	1357.420s	10409.437us	1	1	100.00
chip_sw_keymgr_sideload_kmac				1	1	100.00
	chip_sw_keymgr_sideload_kmac	1641.270s	12179.261us	1	1	100.00
chip_sw_keymgr_sideload_aes				1	1	100.00
	chip_sw_keymgr_sideload_aes	691.340s	7817.862us	1	1	100.00
chip_sw_keymgr_sideload_otbn				1	1	100.00
	chip_sw_keymgr_sideload_otbn	2343.060s	12436.679us	1	1	100.00
chip_sw_kmac_enc				3	3	100.00
	chip_sw_kmac_mode_cshake	163.580s	2805.824us	1	1	100.00
	chip_sw_kmac_mode_kmac	175.690s	3129.563us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	179.050s	2912.725us	1	1	100.00
chip_sw_kmac_app_keymgr				1	1	100.00
	chip_sw_keymgr_key_derivation	1579.340s	11814.903us	1	1	100.00
chip_sw_kmac_app_lc				1	1	100.00
	chip_sw_lc_ctrl_transition	605.420s	11243.879us	1	1	100.00
chip_sw_kmac_app_rom				1	1	100.00
	chip_sw_kmac_app_rom	162.460s	3329.325us	1	1	100.00
chip_sw_kmac_entropy				1	1	100.00
	chip_sw_kmac_entropy	492.980s	5170.957us	1	1	100.00
chip_sw_kmac_idle				1	1	100.00
	chip_sw_kmac_idle	170.860s	3391.437us	1	1	100.00
chip_sw_lc_ctrl_alert_handler_escalation				1	1	100.00
	chip_sw_alert_handler_escalation	347.430s	4872.644us	1	1	100.00
chip_sw_lc_ctrl_jtag_access				3	3	100.00
	chip_tap_straps_dev	509.890s	8237.686us	1	1	100.00
	chip_tap_straps_rma	251.220s	4810.379us	1	1	100.00
	chip_tap_straps_prod	86.480s	3114.764us	1	1	100.00
chip_sw_lc_ctrl_otp_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	167.520s	3377.070us	1	1	100.00
chip_sw_lc_ctrl_init				1	1	100.00
	chip_sw_lc_ctrl_transition	605.420s	11243.879us	1	1	100.00
chip_sw_lc_ctrl_transitions				1	1	100.00
	chip_sw_lc_ctrl_transition	605.420s	11243.879us	1	1	100.00
chip_sw_lc_ctrl_kmac_req				1	1	100.00
	chip_sw_lc_ctrl_transition	605.420s	11243.879us	1	1	100.00
chip_sw_lc_ctrl_key_div				1	1	100.00
	chip_sw_keymgr_key_derivation_prod	1208.980s	9611.912us	1	1	100.00
chip_sw_lc_ctrl_broadcast				19	22	86.36
	chip_sw_flash_ctrl_lc_rw_en	116.250s	2528.788us	0	1	0.00
	chip_sw_flash_rma_unlocked	3838.720s	43854.948us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	236.750s	3488.531us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	462.910s	6170.686us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	467.140s	6303.857us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	432.410s	6301.484us	0	1	0.00
	chip_sw_lc_ctrl_transition	605.420s	11243.879us	1	1	100.00
	chip_sw_keymgr_key_derivation	1579.340s	11814.903us	1	1	100.00
	chip_sw_rom_ctrl_integrity_check	335.010s	9617.744us	1	1	100.00
	chip_sw_sram_ctrl_execution_main	415.620s	6897.534us	1	1	100.00
	chip_prim_tl_access	178.170s	5899.388us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	330.290s	6988.777us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	362.390s	4106.376us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	345.310s	4125.805us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	406.820s	3939.254us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	380.230s	5176.989us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	405.120s	4270.261us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	395.360s	5154.683us	1	1	100.00
	chip_tap_straps_dev	509.890s	8237.686us	1	1	100.00
	chip_tap_straps_rma	251.220s	4810.379us	1	1	100.00
	chip_tap_straps_prod	86.480s	3114.764us	1	1	100.00
	chip_rv_dm_lc_disabled	46.160s	2441.176us	0	1	0.00
chip_lc_scrap				4	4	100.00
	chip_sw_lc_ctrl_rma_to_scrap	206.940s	3598.610us	1	1	100.00
	chip_sw_lc_ctrl_raw_to_scrap	75.720s	3104.238us	1	1	100.00
	chip_sw_lc_ctrl_test_locked0_to_scrap	84.860s	3511.052us	1	1	100.00
	chip_sw_lc_ctrl_rand_to_scrap	202.550s	3515.328us	1	1	100.00
chip_lc_test_locked				1	2	50.00
	chip_sw_lc_walkthrough_testunlocks	1551.620s	32270.057us	1	1	100.00
	chip_rv_dm_lc_disabled	46.160s	2441.176us	0	1	0.00
chip_sw_lc_walkthrough				2	5	40.00
	chip_sw_lc_walkthrough_dev	655.640s	8809.996us	0	1	0.00
	chip_sw_lc_walkthrough_prod	735.730s	11280.841us	0	1	0.00
	chip_sw_lc_walkthrough_prodend	593.310s	10386.687us	1	1	100.00
	chip_sw_lc_walkthrough_rma	354.970s	5818.918us	0	1	0.00
	chip_sw_lc_walkthrough_testunlocks	1551.620s	32270.057us	1	1	100.00
chip_sw_lc_ctrl_volatile_raw_unlock				2	3	66.67
	chip_sw_lc_ctrl_volatile_raw_unlock	62.370s	2103.441us	1	1	100.00
	chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	64.410s	2919.204us	1	1	100.00
	rom_volatile_raw_unlock	110.439s	0.000us	0	1	0.00
chip_sw_otbn_op				2	2	100.00
	chip_sw_otbn_ecdsa_op_irq	3571.660s	16967.705us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3824.590s	20382.493us	1	1	100.00
chip_sw_otbn_rnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	546.750s	6657.076us	1	1	100.00
chip_sw_otbn_urnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	546.750s	6657.076us	1	1	100.00
chip_sw_otbn_idle				1	1	100.00
	chip_sw_otbn_randomness	546.750s	6657.076us	1	1	100.00
chip_sw_otbn_mem_scramble				1	1	100.00
	chip_sw_otbn_mem_scramble	264.720s	4157.815us	1	1	100.00
chip_otp_ctrl_init				1	1	100.00
	chip_sw_lc_ctrl_transition	605.420s	11243.879us	1	1	100.00
chip_sw_otp_ctrl_keys				5	5	100.00
	chip_sw_flash_init	1117.370s	22194.164us	1	1	100.00
	chip_sw_otbn_mem_scramble	264.720s	4157.815us	1	1	100.00
	chip_sw_keymgr_key_derivation	1579.340s	11814.903us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	370.020s	5198.899us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	168.080s	2759.737us	1	1	100.00
chip_sw_otp_ctrl_entropy				5	5	100.00
	chip_sw_flash_init	1117.370s	22194.164us	1	1	100.00
	chip_sw_otbn_mem_scramble	264.720s	4157.815us	1	1	100.00
	chip_sw_keymgr_key_derivation	1579.340s	11814.903us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	370.020s	5198.899us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	168.080s	2759.737us	1	1	100.00
chip_sw_otp_ctrl_program				1	1	100.00
	chip_sw_lc_ctrl_transition	605.420s	11243.879us	1	1	100.00
chip_sw_otp_ctrl_program_error				1	1	100.00
	chip_sw_lc_ctrl_program_error	343.560s	4629.460us	1	1	100.00
chip_sw_otp_ctrl_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	167.520s	3377.070us	1	1	100.00
chip_sw_otp_ctrl_lc_signals				5	6	83.33
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	236.750s	3488.531us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	462.910s	6170.686us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	467.140s	6303.857us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	432.410s	6301.484us	0	1	0.00
	chip_sw_lc_ctrl_transition	605.420s	11243.879us	1	1	100.00
	chip_prim_tl_access	178.170s	5899.388us	1	1	100.00
chip_sw_otp_prim_tl_access				1	1	100.00
	chip_prim_tl_access	178.170s	5899.388us	1	1	100.00
chip_sw_otp_ctrl_dai_lock				1	1	100.00
	chip_sw_otp_ctrl_dai_lock	836.290s	8156.069us	1	1	100.00
chip_sw_pwrmgr_external_full_reset				1	1	100.00
	chip_sw_pwrmgr_full_aon_reset	263.500s	7508.417us	1	1	100.00
chip_sw_pwrmgr_random_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_wake_ups	870.010s	24173.002us	1	1	100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_all_wake_ups	254.720s	7476.964us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_por_reset				0	1	0.00
	chip_sw_pwrmgr_deep_sleep_por_reset	312.310s	7630.198us	0	1	0.00
chip_sw_pwrmgr_normal_sleep_por_reset				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_por_reset	378.450s	6210.542us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_all_wake_ups	670.550s	24079.060us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs				0	2	0.00
	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	357.230s	9688.863us	0	1	0.00
	chip_sw_aon_timer_wdog_bite_reset	422.820s	8731.740us	0	1	0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	997.070s	11454.670us	1	1	100.00
chip_sw_pwrmgr_wdog_reset				1	1	100.00
	chip_sw_pwrmgr_wdog_reset	351.340s	5609.642us	1	1	100.00
chip_sw_pwrmgr_aon_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_full_aon_reset	263.500s	7508.417us	1	1	100.00
chip_sw_pwrmgr_main_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_main_power_glitch_reset	185.260s	3364.251us	1	1	100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	508.590s	10916.618us	0	1	0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	367.580s	8401.041us	1	1	100.00
chip_sw_pwrmgr_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_sleep_power_glitch_reset	153.200s	3129.010us	0	1	0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs				0	1	0.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	664.260s	12380.310us	0	1	0.00
chip_sw_pwrmgr_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	691.670s	6741.316us	1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	1081.200s	12577.890us	1	1	100.00
chip_sw_pwrmgr_b2b_sleep_reset_req				1	1	100.00
	chip_sw_pwrmgr_b2b_sleep_reset_req	1627.410s	29294.770us	1	1	100.00
chip_sw_pwrmgr_sleep_disabled				1	1	100.00
	chip_sw_pwrmgr_sleep_disabled	178.740s	3077.751us	1	1	100.00
chip_sw_pwrmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	450.390s	5935.146us	1	1	100.00
chip_sw_rom_access				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	335.010s	9617.744us	1	1	100.00
chip_sw_rom_ctrl_integrity_check				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	335.010s	9617.744us	1	1	100.00
chip_sw_rstmgr_non_sys_reset_info				3	4	75.00
	chip_sw_pwrmgr_all_reset_reqs	1081.200s	12577.890us	1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	664.260s	12380.310us	0	1	0.00
	chip_sw_pwrmgr_wdog_reset	351.340s	5609.642us	1	1	100.00
	chip_sw_pwrmgr_smoketest	245.470s	5313.456us	1	1	100.00
chip_sw_rstmgr_sys_reset_info				1	1	100.00
	chip_rv_dm_ndm_reset_req	284.470s	4411.982us	1	1	100.00
chip_sw_rstmgr_cpu_info				1	1	100.00
	chip_sw_rstmgr_cpu_info	351.620s	6621.043us	1	1	100.00
chip_sw_rstmgr_sw_req_reset				1	1	100.00
	chip_sw_rstmgr_sw_req	309.030s	4995.369us	1	1	100.00
chip_sw_rstmgr_alert_info				1	1	100.00
	chip_sw_rstmgr_alert_info	1072.680s	13736.122us	1	1	100.00
chip_sw_rstmgr_sw_rst				1	1	100.00
	chip_sw_rstmgr_sw_rst	185.710s	3357.818us	1	1	100.00
chip_sw_rstmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	450.390s	5935.146us	1	1	100.00
chip_sw_rstmgr_alert_handler_reset_enables				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	720.240s	6103.315us	1	1	100.00
chip_sw_nmi_irq				1	1	100.00
	chip_sw_rv_core_ibex_nmi_irq	484.090s	5406.790us	1	1	100.00
chip_sw_rv_core_ibex_rnd				1	1	100.00
	chip_sw_rv_core_ibex_rnd	490.140s	4197.006us	1	1	100.00
chip_sw_rv_core_ibex_address_translation				1	1	100.00
	chip_sw_rv_core_ibex_address_translation	166.540s	2461.222us	1	1	100.00
chip_sw_rv_core_ibex_icache_scrambled_access				1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	168.080s	2759.737us	1	1	100.00
chip_sw_rv_core_ibex_fault_dump				1	1	100.00
	chip_sw_rstmgr_cpu_info	351.620s	6621.043us	1	1	100.00
chip_sw_rv_core_ibex_double_fault				1	1	100.00
	chip_sw_rstmgr_cpu_info	351.620s	6621.043us	1	1	100.00
chip_jtag_csr_rw				1	1	100.00
	chip_jtag_csr_rw	697.390s	10085.087us	1	1	100.00
chip_jtag_mem_access				1	1	100.00
	chip_jtag_mem_access	993.620s	13635.802us	1	1	100.00
chip_rv_dm_ndm_reset_req				1	1	100.00
	chip_rv_dm_ndm_reset_req	284.470s	4411.982us	1	1	100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted				0	1	0.00
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	159.690s	2998.487us	0	1	0.00
chip_rv_dm_access_after_wakeup				1	1	100.00
	chip_sw_rv_dm_access_after_wakeup	272.640s	5099.085us	1	1	100.00
chip_sw_rv_dm_jtag_tap_sel				1	1	100.00
	chip_tap_straps_rma	251.220s	4810.379us	1	1	100.00
chip_rv_dm_lc_disabled				0	1	0.00
	chip_rv_dm_lc_disabled	46.160s	2441.176us	0	1	0.00
chip_sw_plic_all_irqs				3	3	100.00
	chip_plic_all_irqs_0	501.460s	5510.789us	1	1	100.00
	chip_plic_all_irqs_10	263.370s	3381.745us	1	1	100.00
	chip_plic_all_irqs_20	352.290s	4820.076us	1	1	100.00
chip_sw_plic_sw_irq				1	1	100.00
	chip_sw_plic_sw_irq	139.330s	3314.411us	1	1	100.00
chip_sw_timer				1	1	100.00
	chip_sw_rv_timer_irq	175.090s	3231.589us	1	1	100.00
chip_sw_spi_device_flash_mode				1	1	100.00
	rom_e2e_smoke	2966.160s	15756.197us	1	1	100.00
chip_sw_spi_device_pass_through				1	1	100.00
	chip_sw_spi_device_pass_through	480.240s	7892.882us	1	1	100.00
chip_sw_spi_device_pass_through_collision				0	1	0.00
	chip_sw_spi_device_pass_through_collision	205.410s	2792.838us	0	1	0.00
chip_sw_spi_device_tpm				1	1	100.00
	chip_sw_spi_device_tpm	195.320s	3077.097us	1	1	100.00
chip_sw_spi_host_tx_rx				1	1	100.00
	chip_sw_spi_host_tx_rx	192.620s	2894.745us	1	1	100.00
chip_sw_sram_scrambled_access				2	2	100.00
	chip_sw_sram_ctrl_scrambled_access	370.020s	5198.899us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	268.060s	3951.135us	1	1	100.00
chip_sw_sleep_sram_ret_contents				2	2	100.00
	chip_sw_sleep_sram_ret_contents_no_scramble	368.510s	8126.853us	1	1	100.00
	chip_sw_sleep_sram_ret_contents_scramble	510.210s	8263.112us	1	1	100.00
chip_sw_sram_execution				1	1	100.00
	chip_sw_sram_ctrl_execution_main	415.620s	6897.534us	1	1	100.00
chip_sw_sram_lc_escalation				2	2	100.00
	chip_sw_all_escalation_resets	450.390s	5935.146us	1	1	100.00
	chip_sw_data_integrity_escalation	357.180s	5081.860us	1	1	100.00
chip_sw_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	691.670s	6741.316us	1	1	100.00
	chip_sw_sysrst_ctrl_reset	1044.240s	23836.216us	1	1	100.00
chip_sw_sysrst_ctrl_inputs				1	1	100.00
	chip_sw_sysrst_ctrl_inputs	141.700s	2335.366us	1	1	100.00
chip_sw_sysrst_ctrl_outputs				1	1	100.00
	chip_sw_sysrst_ctrl_outputs	230.840s	3933.497us	1	1	100.00
chip_sw_sysrst_ctrl_in_irq				1	1	100.00
	chip_sw_sysrst_ctrl_in_irq	324.640s	5316.440us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_wakeup				1	1	100.00
	chip_sw_sysrst_ctrl_reset	1044.240s	23836.216us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_reset				1	1	100.00
	chip_sw_sysrst_ctrl_reset	1044.240s	23836.216us	1	1	100.00
chip_sw_sysrst_ctrl_ec_rst_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	2436.760s	20151.548us	1	1	100.00
chip_sw_sysrst_ctrl_flash_wp_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	2436.760s	20151.548us	1	1	100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup				1	2	50.00
	chip_sw_sysrst_ctrl_ulp_z3_wakeup	315.030s	5757.916us	1	1	100.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3136.370s	34777.099us	0	1	0.00
chip_sw_usbdev_vbus				1	1	100.00
	chip_sw_usbdev_vbus	134.260s	2813.703us	1	1	100.00
chip_sw_usbdev_pullup				1	1	100.00
	chip_sw_usbdev_pullup	131.280s	3167.969us	1	1	100.00
chip_sw_usbdev_aon_pullup				1	1	100.00
	chip_sw_usbdev_aon_pullup	247.800s	3763.491us	1	1	100.00
chip_sw_usbdev_setup_rx				1	1	100.00
	chip_sw_usbdev_setuprx	304.040s	4334.758us	1	1	100.00
chip_sw_usbdev_config_host				1	1	100.00
	chip_sw_usbdev_config_host	958.900s	8062.571us	1	1	100.00
chip_sw_usbdev_pincfg				1	1	100.00
	chip_sw_usbdev_pincfg	5083.790s	32386.913us	1	1	100.00
chip_sw_usbdev_tx_rx				1	1	100.00
	chip_sw_usbdev_dpi	1822.050s	12502.342us	1	1	100.00
chip_sw_usbdev_toggle_restore				1	1	100.00
	chip_sw_usbdev_toggle_restore	160.560s	3408.763us	1	1	100.00

V2S

1/2 passed

50.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_aes_masking_off				1	1	100.00
	chip_sw_aes_masking_off	169.770s	2426.239us	1	1	100.00
chip_sw_rv_core_ibex_lockstep_glitch				0	1	0.00
	chip_sw_rv_core_ibex_lockstep_glitch	169.210s	2819.634us	0	1	0.00

17/26 passed

65.38 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_coremark				1	1	100.00
	chip_sw_coremark	9948.210s	71632.402us	1	1	100.00
chip_sw_power_max_load				1	1	100.00
	chip_sw_power_virus	1082.680s	6424.392us	1	1	100.00
rom_e2e_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	182.380s	3536.352us	0	1	0.00
	rom_e2e_jtag_debug_dev	428.810s	6012.748us	0	1	0.00
	rom_e2e_jtag_debug_rma	175.240s	3811.746us	0	1	0.00
rom_e2e_jtag_inject				0	3	0.00
	rom_e2e_jtag_inject_test_unlocked0	63.430s	2326.181us	0	1	0.00
	rom_e2e_jtag_inject_dev	50.950s	2054.358us	0	1	0.00
	rom_e2e_jtag_inject_rma	98.470s	3067.480us	0	1	0.00
rom_e2e_self_hash				0	1	0.00
	rom_e2e_self_hash	116.593s	0.000us	0	1	0.00
chip_sw_clkmgr_jitter_cycle_measurements				0	1	0.00
	chip_sw_clkmgr_jitter_frequency	294.050s	3875.230us	0	1	0.00
chip_sw_edn_boot_mode				1	1	100.00
	chip_sw_edn_boot_mode	317.370s	3120.590us	1	1	100.00
chip_sw_edn_auto_mode				1	1	100.00
	chip_sw_edn_auto_mode	490.170s	3681.670us	1	1	100.00
chip_sw_edn_sw_mode				1	1	100.00
	chip_sw_edn_sw_mode	742.670s	6699.397us	1	1	100.00
chip_sw_edn_kat				1	1	100.00
	chip_sw_edn_kat	213.810s	2610.223us	1	1	100.00
chip_sw_flash_memory_protection				1	1	100.00
	chip_sw_flash_ctrl_mem_protection	682.920s	5905.299us	1	1	100.00
chip_sw_otp_ctrl_vendor_test_csr_access				1	1	100.00
	chip_sw_otp_ctrl_vendor_test_csr_access	145.930s	3378.101us	1	1	100.00
chip_sw_otp_ctrl_escalation				0	1	0.00
	chip_sw_otp_ctrl_escalation	147.460s	3446.523us	0	1	0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up				1	1	100.00
	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	268.670s	5404.142us	1	1	100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active				1	1	100.00
	chip_sw_pwrmgr_usb_clk_disabled_when_active	287.260s	5058.053us	1	1	100.00
chip_sw_all_resets				1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	1081.200s	12577.890us	1	1	100.00
chip_rv_dm_perform_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	182.380s	3536.352us	0	1	0.00
	rom_e2e_jtag_debug_dev	428.810s	6012.748us	0	1	0.00
	rom_e2e_jtag_debug_rma	175.240s	3811.746us	0	1	0.00
chip_sw_rv_dm_access_after_hw_reset				1	1	100.00
	chip_sw_rv_dm_access_after_escalation_reset	345.570s	4575.410us	1	1	100.00
chip_sw_plic_alerts				1	1	100.00
	chip_sw_all_escalation_resets	450.390s	5935.146us	1	1	100.00
tick_configuration				1	1	100.00
	chip_sw_rv_timer_systick_test	5490.560s	38018.210us	1	1	100.00
counter_wrap				1	1	100.00
	chip_sw_rv_timer_systick_test	5490.560s	38018.210us	1	1	100.00
chip_sw_spi_device_output_when_disabled_or_sleeping				1	1	100.00
	chip_sw_spi_device_pinmux_sleep_retention	165.680s	3478.621us	1	1	100.00
chip_sw_uart_watermarks				1	1	100.00
	chip_sw_uart_tx_rx	417.820s	5055.369us	1	1	100.00
chip_sw_usbdev_stream				1	1	100.00
	chip_sw_usbdev_stream	3155.210s	19158.902us	1	1	100.00

unmapped

7/10 passed

70.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				7	10	70.00
	chip_sival_flash_info_access	233.610s	3130.184us	1	1	100.00
	chip_sw_rstmgr_rst_cnsty_escalation	354.890s	5322.768us	1	1	100.00
	chip_sw_otp_ctrl_rot_auth_config	4.720s	0.000us	0	1	0.00
	chip_sw_otp_ctrl_ecc_error_vendor_test	126.090s	2576.474us	1	1	100.00
	chip_sw_otp_ctrl_descrambling	225.670s	3123.184us	1	1	100.00
	chip_sw_pwrmgr_lowpower_cancel	200.850s	3481.992us	0	1	0.00
	chip_sw_pwrmgr_sleep_wake_5_bug	8.943s	0.000us	0	1	0.00
	chip_sw_flash_ctrl_write_clear	192.800s	3195.471us	1	1	100.00
	ate_bootstrap_flash_erase	6530.940s	45361.149us	1	1	100.00
	ate_bootstrap_disjoint	9469.550s	84997.024us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
	chip_sw_spi_device_pass_through_collision	23935845935995148390614397413729655290261680653708863563764889233803473816342	320	UVM_INFO @ 2792.837694 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
	chip_sw_flash_ctrl_lc_rw_en	37341385377853862016560476876960774582273465480728557813320014780031479007189	309	UVM_INFO @ 2528.787656 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *
	chip_sw_otp_ctrl_lc_signals_rma	43088867969549245477397086233746612871850754216430366677512418406901566740073	342	UVM_INFO @ 6301.484288 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
	chip_sw_otp_ctrl_escalation	112962076400088763172218393168009247172597947799764561619988613113151441302683	316	UVM_ERROR @ 3446.522872 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A UVM_INFO @ 3446.522872 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_csrng_fuse_en_sw_app_read_test	27615251586166394200272259743957562363208816443831109494059533674889731107210	312	UVM_ERROR @ 3084.965198 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A UVM_INFO @ 3084.965198 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode
	chip_sw_otp_ctrl_rot_auth_config	32790225698442832680184450847114393201525185907786424945824725389128241802293	282	UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
	chip_sw_lc_walkthrough_dev	36172088718862141520176113002044663823424580629543892508737460281778770960846	369	UVM_INFO @ 8809.996460 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_prod	112510732548173016428665140042685820120538435720601295341674401098716912937800	369	UVM_INFO @ 11280.840636 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_rma	93073616223159966053276074623948950175808549963548562218377935126033299907859	341	UVM_INFO @ 5818.918106 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))'
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	114708702538689711882820689061355757521932471718482591936837445108445811691558	344	UVM_ERROR @ 12380.310000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 12380.310000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	38592592131114391594755753129630098566714589470968809615000013029848168299616	327	UVM_ERROR @ 9688.863500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 9688.863500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_deep_sleep_por_reset	3203584796163931387440397482329184300283254084050613982948548094514038395469	325	UVM_ERROR @ 7630.197500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 7630.197500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_aon_timer_wdog_bite_reset	85482218643328016211800813197988305695785790735277723175589341864635245759648	319	UVM_ERROR @ 8731.740000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 8731.740000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))'
	chip_sw_pwrmgr_sleep_power_glitch_reset	43742199905202561380248938220045974413355518558301264093002877030144561665613	313	UVM_ERROR @ 3129.009864 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A UVM_INFO @ 3129.009864 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	69886884919176170224671501021678086825868194609240919261862655931638074529667	341	UVM_ERROR @ 10916.617943 us: (rom_ctrl.sv:577) [ASSERT FAILED] PwrmgrDataChk_A UVM_INFO @ 10916.617943 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	23169478039231028000936180879599460650100119672695733325558455352597390409793	332	UVM_INFO @ 34777.098551 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:352)] CHECK-fail: Expect alert *!
	chip_sw_alert_test	70075331399164299838671595033107043331566684017260124679815008318114206750584	307	UVM_INFO @ 3401.609714 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
	chip_sw_alert_handler_lpg_sleep_mode_alerts	67834085741202588259980780078273510312619956560163700127395734747918963907406	308	UVM_INFO @ 2660.087805 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job killed!
	chip_sw_alert_handler_lpg_sleep_mode_pings	97706492364814650270401953667308137044719766870417152121896828765425773811684	None
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted , but saw ).
	chip_tl_errors	20769183933627736184578078132383157651136889740073449664214533241480349275641	217	TL item was: req: (cip_tl_seq_item@33677) { a_addr: 'h105e4 a_data: 'hd5251b2c a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h1a a_opcode: 'h4 a_user: 'h19efd d_param: 'h0 d_source: 'h1a d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 } Reasons for predicted error: '{"Fetch from CSR"} . UVM_INFO @ 2777.292788 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected
	chip_sw_clkmgr_jitter_frequency	1004862987955783430135219021125437407996606284156385505017624594684316592099	343	UVM_INFO @ 3875.230326 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [pwrmgr_lowpower_cancel_test_sim_dv(sw/device/tests/pwrmgr_lowpower_cancel_test.c:78)] CHECK-fail: Timed out after * usec (* CPU cycles) waiting for !get_wakeup_status()
	chip_sw_pwrmgr_lowpower_cancel	10241831711371619080776928460432762406135430280573859634305326201372009273832	317	UVM_INFO @ 3481.992466 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']
	chip_sw_pwrmgr_sleep_wake_5_bug	76370821748967590589613668300618644066701931154668036689531864597167811700159	None	---- STDOUT ---- ---- STDERR ---- WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	18917863690658408030148719336365960054531646246941121867456540518023227563228	None	Another command (pid=587974) is running. Waiting for it to complete on the server (server_pid=251960)... Another command (pid=580081) is running. Waiting for it to complete on the server (server_pid=251960)... Another command (pid=601327) is running. Waiting for it to complete on the server (server_pid=251960)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_dev	85576556626641247031818698481084618065899054945703071131629813903783287556168	None	Another command (pid=396733) is running. Waiting for it to complete on the server (server_pid=251960)... Another command (pid=552035) is running. Waiting for it to complete on the server (server_pid=251960)... Another command (pid=460011) is running. Waiting for it to complete on the server (server_pid=251960)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_prod	99220215589991574982514085761618001452108576256195205369978318004634193099301	None	Another command (pid=613652) is running. Waiting for it to complete on the server (server_pid=251960)... Another command (pid=595658) is running. Waiting for it to complete on the server (server_pid=251960)... Another command (pid=610215) is running. Waiting for it to complete on the server (server_pid=251960)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_prod_end	98888917071217180134110032310292867515268652867597875717802671129136050641932	None	Another command (pid=580081) is running. Waiting for it to complete on the server (server_pid=251960)... Another command (pid=601327) is running. Waiting for it to complete on the server (server_pid=251960)... Another command (pid=396733) is running. Waiting for it to complete on the server (server_pid=251960)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_rma	94206584238200463940869012946813127644016644225524173221218705104243975348514	None	Another command (pid=610719) is running. Waiting for it to complete on the server (server_pid=251960)... Another command (pid=588300) is running. Waiting for it to complete on the server (server_pid=251960)... Another command (pid=516124) is running. Waiting for it to complete on the server (server_pid=251960)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	61736808661573380100678669948922946268007461695779788236533743218432662260465	None	Another command (pid=364838) is running. Waiting for it to complete on the server (server_pid=251960)... Another command (pid=554824) is running. Waiting for it to complete on the server (server_pid=251960)... Another command (pid=556042) is running. Waiting for it to complete on the server (server_pid=251960)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_dev	62606938193908692912202900797515195493304768809779647612182343192253897638720	None	---- STDERR ---- Another command (pid=556042) is running. Waiting for it to complete on the server (server_pid=251960)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_prod	70463618792263472409994614895813118975633119476297818104967537983651790528371	None	Another command (pid=732479) is running. Waiting for it to complete on the server (server_pid=251960)... Another command (pid=736032) is running. Waiting for it to complete on the server (server_pid=251960)... Another command (pid=656616) is running. Waiting for it to complete on the server (server_pid=251960)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	44940902587496606202520744423564930680463754287864955938864908978876862229843	None	Another command (pid=424303) is running. Waiting for it to complete on the server (server_pid=251960)... Another command (pid=580081) is running. Waiting for it to complete on the server (server_pid=251960)... Another command (pid=601327) is running. Waiting for it to complete on the server (server_pid=251960)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_rma	47768897615462217834972857578198754298283741285758583383412888943426428989925	None	Another command (pid=583551) is running. Waiting for it to complete on the server (server_pid=251960)... Another command (pid=586675) is running. Waiting for it to complete on the server (server_pid=251960)... Another command (pid=424303) is running. Waiting for it to complete on the server (server_pid=251960)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	30738082754824230744863223147674871974034571050263756846982174419950995940356	None	Another command (pid=601327) is running. Waiting for it to complete on the server (server_pid=251960)... Another command (pid=396733) is running. Waiting for it to complete on the server (server_pid=251960)... Another command (pid=588592) is running. Waiting for it to complete on the server (server_pid=251960)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_dev	87389766535863542800590556461763080736457097429598643244233653325901620158223	None	Another command (pid=570112) is running. Waiting for it to complete on the server (server_pid=251960)... Another command (pid=568885) is running. Waiting for it to complete on the server (server_pid=251960)... Another command (pid=568212) is running. Waiting for it to complete on the server (server_pid=251960)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_prod	59594237404053795179734453323370283029584926540873219204839991512647305558504	None	Another command (pid=379816) is running. Waiting for it to complete on the server (server_pid=251960)... Another command (pid=562565) is running. Waiting for it to complete on the server (server_pid=251960)... Another command (pid=552998) is running. Waiting for it to complete on the server (server_pid=251960)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	88784380806975989401666930008804631377643633243902830810023901440312198660652	None	Another command (pid=461551) is running. Waiting for it to complete on the server (server_pid=251960)... Another command (pid=564985) is running. Waiting for it to complete on the server (server_pid=251960)... Another command (pid=567762) is running. Waiting for it to complete on the server (server_pid=251960)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_rma	63501544438673104217709464365996685933638654056984767804284772305690495238657	None	Another command (pid=443015) is running. Waiting for it to complete on the server (server_pid=251960)... Another command (pid=567762) is running. Waiting for it to complete on the server (server_pid=251960)... Another command (pid=566529) is running. Waiting for it to complete on the server (server_pid=251960)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_test_unlocked0	97248457932056120065036814377247834648920865351393258900099884982918374001160	None	Another command (pid=443015) is running. Waiting for it to complete on the server (server_pid=251960)... Another command (pid=567762) is running. Waiting for it to complete on the server (server_pid=251960)... Another command (pid=566529) is running. Waiting for it to complete on the server (server_pid=251960)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_dev	107126014748566616823012281165460229038234728651762713797571437199413178752256	None	Another command (pid=443563) is running. Waiting for it to complete on the server (server_pid=251960)... Another command (pid=396388) is running. Waiting for it to complete on the server (server_pid=251960)... Another command (pid=397509) is running. Waiting for it to complete on the server (server_pid=251960)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_prod	105312085968302863649505064538760022635846307788330483639589462916754604867331	None	---- STDERR ---- Another command (pid=443563) is running. Waiting for it to complete on the server (server_pid=251960)... Another command (pid=397509) is running. Waiting for it to complete on the server (server_pid=251960)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_prod_end	107429998886883888403437419322794591853437980469245014446586172441166189688906	None	Another command (pid=591184) is running. Waiting for it to complete on the server (server_pid=251960)... Another command (pid=610719) is running. Waiting for it to complete on the server (server_pid=251960)... Another command (pid=588300) is running. Waiting for it to complete on the server (server_pid=251960)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_rma	65149634065211842119405608535086363210311793039953279334161936015295722642841	None	Another command (pid=554824) is running. Waiting for it to complete on the server (server_pid=251960)... Another command (pid=556042) is running. Waiting for it to complete on the server (server_pid=251960)... Another command (pid=562304) is running. Waiting for it to complete on the server (server_pid=251960)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_volatile_raw_unlock	86328071893663225538912260304583877672721154443021497444688097109956688316185	None	Another command (pid=375453) is running. Waiting for it to complete on the server (server_pid=251960)... Another command (pid=365697) is running. Waiting for it to complete on the server (server_pid=251960)... Another command (pid=443563) is running. Waiting for it to complete on the server (server_pid=251960)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_raw_unlock	79169307862647911417934660843794953368943848102336909468526516051740687387288	None	Another command (pid=566529) is running. Waiting for it to complete on the server (server_pid=251960)... Another command (pid=569623) is running. Waiting for it to complete on the server (server_pid=251960)... Another command (pid=570112) is running. Waiting for it to complete on the server (server_pid=251960)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_self_hash	26692922284714722083750254161554160554296203487934716764292373751916951838160	None	Another command (pid=365697) is running. Waiting for it to complete on the server (server_pid=251960)... Another command (pid=414574) is running. Waiting for it to complete on the server (server_pid=251960)... Another command (pid=443563) is running. Waiting for it to complete on the server (server_pid=251960)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Error-[NOA] Null object access
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	41089783693700204086396406024125636897718132322728103734140860622517378640576	327	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_debug_test_unlocked0	53955387940750047903733497195710565872504439525495028578950270300697338138864	319	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_debug_dev	111534111830195772032844883619610759993607016243314633151584599651606725676141	352	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_debug_rma	12774067308807115373061422514300229894240450861975392989123350946517481758921	319	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_test_unlocked0	15864184774974510645467044195271927609559988127067885697733031623455118505802	307	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_dev	109305122981202549436218901280874009151877846783099842509795797319313811926253	303	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_rma	33576669707814628056603694168716858339439052384624203377125604337246406118435	307	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
UVM_ERROR @ * us: (cip_base_vseq.sv:649) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [] vs []) addr read out mismatch
	chip_rv_dm_lc_disabled	67799321494703374231386267533332762028816603579836203360002241594623800723572	215	UVM_INFO @ 2441.176449 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:738) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [] vs [*]) Major alert did not match expectation.
	chip_sw_rv_core_ibex_lockstep_glitch	14130028206051114726770063893259687830581434530140638649513778807883007596161	327	UVM_INFO @ 2819.633560 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
	chip_sw_power_idle_load	43507478217254554659570565627905420313942253571961301558665324158349704576646	312	UVM_INFO @ 3105.253000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : *
	chip_sw_power_sleep_load	105434651267071293463844877051451911209416352906616225564778197052676920583806	318	UVM_INFO @ 3795.715500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *
	chip_sw_ast_clk_rst_inputs	82331648343774770607163458597860723385942475859746568692242769681463433305415	327	UVM_INFO @ 10813.441203 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_.signed..scr.vmem could not be opened for r mode
	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	103317059142807963929063754474921725914552048232688174626241703458109253853929	364	UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	3051171642649800633332194332696137974041761550171355897075328861372923334465	326	UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_.signed..scr.vmem could not be opened for r mode
	rom_e2e_sigverify_always_a_bad_b_bad_dev	9953038941612404735816886091197688683643580306016383094684404159741486228473	366	UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_dev	46152384442311786189584355346479102883162801597088079027059355459219790628556	328	UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_.signed..scr.vmem could not be opened for r mode
	rom_e2e_sigverify_always_a_bad_b_bad_prod	64922552323145397760513827291666243531168679427287655612681607131289409035324	366	UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_bad_prod_end	86976316282758294881663838365721786686129658845114403486205948158162611507371	366	UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_bad_rma	108607785948150404791020521721022089962641506166796502931864568155493101924119	365	UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_prod	69566140054120270788068086809022326900385965101236915885847514066052654690906	326	UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	4248406442808941709256916647756819322263654663867132759795277441943811743788	328	UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_rma	912739564455562853508544734246807560636882830944878795953430960514210906350	328	UVM_INFO @ 10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_.signed..scr.vmem could not be opened for r mode
	rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	112772578428522554866809938535262052421180036435754924070039122533456875836941	325	UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_.signed..scr.vmem could not be opened for r mode
	rom_e2e_sigverify_always_a_nothing_b_bad_dev	50426196584497929685726537606861330136620336226149193844871550531559695983224	328	UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_.signed..scr.vmem could not be opened for r mode
	rom_e2e_sigverify_always_a_nothing_b_bad_prod	11578799764846944375551030934596909735588180628007114215798952798011720054132	328	UVM_INFO @ 10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	97415618379316428781198744753015134604199880178134190993084635598148085248329	326	UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_nothing_b_bad_rma	65245651052220578364373780105859306341960354870850549133705793831975577789639	326	UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *
	rom_e2e_keymgr_init_rom_ext_meas	52710175822831563667690564106058527691406279242975019006795437871794989094912	319	UVM_INFO @ 19439.679640 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '$stable(key_data_i)'
	rom_keymgr_functest	33112863341680579495458568895574851690842009821617571963938362595497145620846	327	UVM_ERROR @ 4537.874525 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M UVM_INFO @ 4537.874525 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---