Simulation Results: clkmgr

 
21/04/2026 00:01:59 DVSim: v1.32.0 sha: 089baca json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.27 %
  • code
  • 98.17 %
  • assert
  • 95.20 %
  • func
  • 86.45 %
  • line
  • 98.97 %
  • branch
  • 98.57 %
  • cond
  • 94.11 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
91.67%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.920s 97.625us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.800s 59.402us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 0.750s 21.707us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 4.450s 466.510us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 1.620s 208.584us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 1.400s 134.083us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 0.750s 21.707us 1 1 100.00
clkmgr_csr_aliasing 1.620s 208.584us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.700s 17.014us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 1.680s 139.487us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.780s 35.948us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.770s 12.045us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.920s 97.625us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 1.840s 359.596us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 6.850s 1456.401us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 1.840s 359.596us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 34.180s 10750.828us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.950s 34.167us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 2.220s 134.140us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 2.220s 134.140us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.800s 59.402us 1 1 100.00
clkmgr_csr_rw 0.750s 21.707us 1 1 100.00
clkmgr_csr_aliasing 1.620s 208.584us 1 1 100.00
clkmgr_same_csr_outstanding 1.160s 37.038us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.800s 59.402us 1 1 100.00
clkmgr_csr_rw 0.750s 21.707us 1 1 100.00
clkmgr_csr_aliasing 1.620s 208.584us 1 1 100.00
clkmgr_same_csr_outstanding 1.160s 37.038us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 1 2 50.00
clkmgr_sec_cm 0.860s 10.592us 0 1 0.00
clkmgr_tl_intg_err 1.520s 67.380us 1 1 100.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.880s 260.135us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.880s 260.135us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.880s 260.135us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.880s 260.135us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
clkmgr_shadow_reg_errors_with_csr_rw 2.290s 123.196us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
clkmgr_tl_intg_err 1.520s 67.380us 1 1 100.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 1.840s 359.596us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 6.850s 1456.401us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.880s 260.135us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.970s 23.986us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 0.770s 16.436us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.880s 14.021us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.800s 17.610us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.740s 21.695us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 0.750s 21.707us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 0.860s 10.592us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 0.750s 21.707us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 0.750s 21.707us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 0.860s 10.592us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 3.550s 1265.145us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 39.470s 4362.935us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1022) virtual_sequencer [clkmgr_common_vseq] expect alert:fatal_fault to fire
clkmgr_sec_cm 71828219600233723257277744051098479309101552762392589276429853473093006078817 82
UVM_INFO @ 10592276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---