Simulation Results: csrng

 
21/04/2026 00:01:59 DVSim: v1.32.0 sha: 089baca json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.24 %
  • code
  • 92.20 %
  • assert
  • 92.79 %
  • func
  • 79.72 %
  • block
  • 96.91 %
  • line
  • 97.62 %
  • branch
  • 92.25 %
  • toggle
  • 93.24 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 3.000s 82.319us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 1.000s 41.618us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 2.000s 31.708us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 9.000s 263.853us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 2.000s 29.625us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 2.000s 60.675us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 2.000s 31.708us 1 1 100.00
csrng_csr_aliasing 2.000s 29.625us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 4.000s 70.284us 1 1 100.00
alerts 1 1 100.00
csrng_alert 8.000s 216.780us 1 1 100.00
err 1 1 100.00
csrng_err 3.000s 37.351us 1 1 100.00
cmds 1 1 100.00
csrng_cmds 75.000s 4686.018us 1 1 100.00
life cycle 1 1 100.00
csrng_cmds 75.000s 4686.018us 1 1 100.00
stress_all 1 1 100.00
csrng_stress_all 217.000s 13538.120us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 14.442us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 71.521us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 5.000s 180.425us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 5.000s 180.425us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 1.000s 41.618us 1 1 100.00
csrng_csr_rw 2.000s 31.708us 1 1 100.00
csrng_csr_aliasing 2.000s 29.625us 1 1 100.00
csrng_same_csr_outstanding 2.000s 168.344us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 1.000s 41.618us 1 1 100.00
csrng_csr_rw 2.000s 31.708us 1 1 100.00
csrng_csr_aliasing 2.000s 29.625us 1 1 100.00
csrng_same_csr_outstanding 2.000s 168.344us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 2.000s 137.679us 1 1 100.00
csrng_tl_intg_err 4.000s 105.505us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_regwen 2.000s 21.261us 1 1 100.00
csrng_csr_rw 2.000s 31.708us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 8.000s 216.780us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 217.000s 13538.120us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 4.000s 70.284us 1 1 100.00
csrng_err 3.000s 37.351us 1 1 100.00
csrng_sec_cm 2.000s 137.679us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 4.000s 70.284us 1 1 100.00
csrng_err 3.000s 37.351us 1 1 100.00
csrng_sec_cm 2.000s 137.679us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 4.000s 70.284us 1 1 100.00
csrng_err 3.000s 37.351us 1 1 100.00
csrng_sec_cm 2.000s 137.679us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 4.000s 70.284us 1 1 100.00
csrng_err 3.000s 37.351us 1 1 100.00
csrng_sec_cm 2.000s 137.679us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 4.000s 70.284us 1 1 100.00
csrng_err 3.000s 37.351us 1 1 100.00
csrng_sec_cm 2.000s 137.679us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 8.000s 216.780us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 4.000s 70.284us 1 1 100.00
csrng_err 3.000s 37.351us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 217.000s 13538.120us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 8.000s 216.780us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 4.000s 105.505us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 4.000s 70.284us 1 1 100.00
csrng_err 3.000s 37.351us 1 1 100.00
csrng_sec_cm 2.000s 137.679us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 4.000s 70.284us 1 1 100.00
csrng_err 3.000s 37.351us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 4.000s 70.284us 1 1 100.00
csrng_err 3.000s 37.351us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 4.000s 70.284us 1 1 100.00
csrng_err 3.000s 37.351us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 4.000s 70.284us 1 1 100.00
csrng_err 3.000s 37.351us 1 1 100.00
csrng_sec_cm 2.000s 137.679us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 4.000s 70.284us 1 1 100.00
csrng_err 3.000s 37.351us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 0.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
Job killed!
csrng_stress_all_with_rand_reset 95547012713470282364719647983929680734917273388104264902116438194963794871536 None