Simulation Results: edn/edn0

 
21/04/2026 00:01:59 DVSim: v1.32.0 sha: 089baca json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.00 %
  • code
  • 86.63 %
  • assert
  • 95.44 %
  • func
  • 81.94 %
  • line
  • 98.32 %
  • branch
  • 94.28 %
  • cond
  • 88.80 %
  • toggle
  • 93.16 %
  • FSM
  • 58.60 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.760s 108.915us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.830s 61.086us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.800s 46.139us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.320s 60.792us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.110s 27.654us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.570s 161.739us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.800s 46.139us 1 1 100.00
edn_csr_aliasing 1.110s 27.654us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.170s 33.392us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.170s 33.392us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.170s 33.392us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.040s 21.511us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.970s 41.498us 1 1 100.00
errs 1 1 100.00
edn_err 0.840s 21.246us 1 1 100.00
disable 2 2 100.00
edn_disable 0.980s 33.416us 1 1 100.00
edn_disable_auto_req_mode 1.160s 34.651us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.690s 295.190us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.820s 56.080us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.000s 28.646us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.160s 75.292us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.160s 75.292us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.830s 61.086us 1 1 100.00
edn_csr_rw 0.800s 46.139us 1 1 100.00
edn_csr_aliasing 1.110s 27.654us 1 1 100.00
edn_same_csr_outstanding 1.100s 78.611us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.830s 61.086us 1 1 100.00
edn_csr_rw 0.800s 46.139us 1 1 100.00
edn_csr_aliasing 1.110s 27.654us 1 1 100.00
edn_same_csr_outstanding 1.100s 78.611us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 4.290s 293.694us 1 1 100.00
edn_tl_intg_err 1.500s 80.461us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.780s 37.922us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.970s 41.498us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.290s 293.694us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.290s 293.694us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 4.290s 293.694us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 4.290s 293.694us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.970s 41.498us 1 1 100.00
edn_sec_cm 4.290s 293.694us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.970s 41.498us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.500s 80.461us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 32.640s 1959.224us 1 1 100.00