Simulation Results: edn/edn1

 
21/04/2026 00:01:59 DVSim: v1.32.0 sha: 089baca json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.90 %
  • code
  • 83.39 %
  • assert
  • 97.14 %
  • func
  • 74.16 %
  • line
  • 97.95 %
  • branch
  • 92.86 %
  • cond
  • 87.08 %
  • toggle
  • 95.89 %
  • FSM
  • 43.18 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.840s 30.784us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.840s 31.922us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.790s 110.549us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.340s 213.209us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.580s 40.836us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.030s 20.034us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.790s 110.549us 1 1 100.00
edn_csr_aliasing 1.580s 40.836us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.060s 44.602us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.060s 44.602us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.060s 44.602us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.770s 31.491us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.930s 80.895us 1 1 100.00
errs 1 1 100.00
edn_err 0.950s 69.441us 1 1 100.00
disable 2 2 100.00
edn_disable 0.850s 60.091us 1 1 100.00
edn_disable_auto_req_mode 0.980s 48.352us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.070s 45.375us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.760s 27.824us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.960s 13.858us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.260s 107.572us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.260s 107.572us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.840s 31.922us 1 1 100.00
edn_csr_rw 0.790s 110.549us 1 1 100.00
edn_csr_aliasing 1.580s 40.836us 1 1 100.00
edn_same_csr_outstanding 0.920s 22.021us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.840s 31.922us 1 1 100.00
edn_csr_rw 0.790s 110.549us 1 1 100.00
edn_csr_aliasing 1.580s 40.836us 1 1 100.00
edn_same_csr_outstanding 0.920s 22.021us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 2.280s 677.305us 1 1 100.00
edn_tl_intg_err 1.290s 353.977us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.870s 20.621us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.930s 80.895us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.280s 677.305us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.280s 677.305us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.280s 677.305us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.280s 677.305us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.930s 80.895us 1 1 100.00
edn_sec_cm 2.280s 677.305us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.930s 80.895us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.290s 353.977us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
edn_stress_all_with_rand_reset 22.060s 1588.453us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
edn_stress_all_with_rand_reset 105996887689331976231334507610708867813949274983441141444762139597361661067521 175
UVM_INFO @ 1588452929 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---