Simulation Results: flash_ctrl

 
21/04/2026 00:01:59 DVSim: v1.32.0 sha: 089baca json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.61 %
  • code
  • 94.59 %
  • assert
  • 96.67 %
  • func
  • 95.57 %
  • line
  • 96.07 %
  • branch
  • 97.21 %
  • cond
  • 93.80 %
  • toggle
  • 98.09 %
  • FSM
  • 87.76 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 50.890s 45.196us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 12.330s 19.663us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 22.170s 171.727us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 8.060s 70.423us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 44.230s 6283.667us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 18.720s 424.139us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 7.840s 87.903us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 8.060s 70.423us 1 1 100.00
flash_ctrl_csr_aliasing 18.720s 424.139us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 6.080s 50.361us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 9.650s 42.723us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 9.550s 77.749us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 16.130s 52.332us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1317.090s 355280.710us 1 1 100.00
flash_ctrl_hw_rma_reset 596.100s 210167.720us 1 1 100.00
flash_ctrl_lcmgr_intg 12.430s 38.361us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1187.170s 504386.644us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 171.330s 5576.802us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 5.620s 53.137us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 1811.370s 189960.826us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 104.750s 2721.746us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 16.730s 69.290us 1 1 100.00
flash_ctrl_rw_evict_all_en 13.320s 28.163us 1 1 100.00
flash_ctrl_re_evict 15.270s 931.202us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 140.540s 10382.822us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 140.540s 10382.822us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 183.250s 32347.724us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 12.620s 395.615us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 362.350s 1570.875us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 296.100s 7595.258us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 288.490s 1550.476us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 891.560s 880.698us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 7.600s 22.224us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 143.880s 5102.410us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 10.360s 20.513us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 8.410s 17.781us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 350.040s 503.822us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 67.050s 9569.379us 1 1 100.00
flash_ctrl_otp_reset 56.120s 72.645us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1317.090s 355280.710us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 123.590s 2133.938us 1 1 100.00
flash_ctrl_intr_wr 53.710s 3029.434us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 106.670s 11822.184us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 149.520s 27611.429us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 45.760s 1534.374us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 37.810s 7139.855us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 11.850s 26.858us 1 1 100.00
flash_ctrl_ro_derr 78.040s 600.568us 1 1 100.00
flash_ctrl_rw_derr 180.170s 25820.851us 1 1 100.00
flash_ctrl_derr_detect 135.920s 1695.597us 1 1 100.00
flash_ctrl_integrity 458.530s 16955.608us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 10.250s 25.483us 1 1 100.00
flash_ctrl_ro_serr 95.340s 1604.023us 1 1 100.00
flash_ctrl_rw_serr 135.880s 2864.685us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 52.000s 5627.324us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 83.580s 16300.609us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 111.150s 2328.466us 1 1 100.00
flash_ctrl_write_word_sweep 7.270s 149.818us 1 1 100.00
flash_ctrl_read_word_sweep 10.600s 326.864us 1 1 100.00
flash_ctrl_ro 85.950s 1414.308us 1 1 100.00
flash_ctrl_rw 429.580s 28359.330us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 24.830s 623.556us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 753.360s 165746.311us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 90.730s 10019.647us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 6.590s 61.915us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 7.540s 20.026us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 12.420s 78.262us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 12.420s 78.262us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 22.170s 171.727us 1 1 100.00
flash_ctrl_csr_rw 8.060s 70.423us 1 1 100.00
flash_ctrl_csr_aliasing 18.720s 424.139us 1 1 100.00
flash_ctrl_same_csr_outstanding 14.060s 868.031us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 22.170s 171.727us 1 1 100.00
flash_ctrl_csr_rw 8.060s 70.423us 1 1 100.00
flash_ctrl_csr_aliasing 18.720s 424.139us 1 1 100.00
flash_ctrl_same_csr_outstanding 14.060s 868.031us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 9.220s 77.251us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 9.220s 77.251us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 9.220s 77.251us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 9.220s 77.251us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 38.390s 103.513us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_sec_cm 1461.940s 2088.252us 1 1 100.00
flash_ctrl_tl_intg_err 143.000s 1762.870us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 143.000s 1762.870us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 143.000s 1762.870us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 14.970s 65.302us 1 1 100.00
flash_ctrl_wr_intg 11.720s 45.851us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 50.890s 45.196us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 56.120s 72.645us 1 1 100.00
flash_ctrl_disable 10.360s 20.513us 1 1 100.00
flash_ctrl_sec_info_access 43.050s 3850.251us 1 1 100.00
flash_ctrl_connect 8.410s 17.781us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 5.370s 137.086us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.060s 70.423us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 9.220s 77.251us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.060s 70.423us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 9.220s 77.251us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 8.060s 70.423us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 9.220s 77.251us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 10.360s 20.513us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 14.970s 65.302us 1 1 100.00
flash_ctrl_access_after_disable 6.200s 39.649us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 14.490s 38.892us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 10.360s 20.513us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 12.620s 395.615us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 429.580s 28359.330us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 135.880s 2864.685us 1 1 100.00
flash_ctrl_rw_derr 180.170s 25820.851us 1 1 100.00
flash_ctrl_integrity 458.530s 16955.608us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1317.090s 355280.710us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1461.940s 2088.252us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1461.940s 2088.252us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1461.940s 2088.252us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1461.940s 2088.252us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 9.500s 948.904us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 6.300s 22.836us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 6.260s 22.864us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1461.940s 2088.252us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1461.940s 2088.252us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1461.940s 2088.252us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 20.900s 140.358us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 108.940s 167.754us 1 1 100.00