Simulation Results: hmac

 
21/04/2026 00:01:59 DVSim: v1.32.0 sha: 089baca json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.45 %
  • code
  • 98.40 %
  • assert
  • 96.70 %
  • func
  • 43.26 %
  • line
  • 99.74 %
  • branch
  • 99.17 %
  • cond
  • 96.01 %
  • toggle
  • 100.00 %
  • FSM
  • 97.06 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 8.260s 854.802us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.730s 19.033us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.700s 19.645us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 12.730s 1606.037us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 6.000s 319.293us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.390s 63.944us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.700s 19.645us 1 1 100.00
hmac_csr_aliasing 6.000s 319.293us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 44.560s 12729.175us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 37.890s 856.059us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 181.270s 5219.129us 1 1 100.00
hmac_test_sha384_vectors 21.220s 239.453us 1 1 100.00
hmac_test_sha512_vectors 354.510s 42777.158us 1 1 100.00
hmac_test_hmac256_vectors 6.700s 402.306us 1 1 100.00
hmac_test_hmac384_vectors 7.630s 501.046us 1 1 100.00
hmac_test_hmac512_vectors 7.790s 1669.851us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 4.470s 300.866us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 521.200s 18588.900us 1 1 100.00
error 1 1 100.00
hmac_error 83.350s 76252.706us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 91.780s 21117.616us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 8.260s 854.802us 1 1 100.00
hmac_long_msg 44.560s 12729.175us 1 1 100.00
hmac_back_pressure 37.890s 856.059us 1 1 100.00
hmac_datapath_stress 521.200s 18588.900us 1 1 100.00
hmac_burst_wr 4.470s 300.866us 1 1 100.00
hmac_stress_all 1418.620s 84853.548us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 8.260s 854.802us 1 1 100.00
hmac_long_msg 44.560s 12729.175us 1 1 100.00
hmac_back_pressure 37.890s 856.059us 1 1 100.00
hmac_datapath_stress 521.200s 18588.900us 1 1 100.00
hmac_wipe_secret 91.780s 21117.616us 1 1 100.00
hmac_test_sha256_vectors 181.270s 5219.129us 1 1 100.00
hmac_test_sha384_vectors 21.220s 239.453us 1 1 100.00
hmac_test_sha512_vectors 354.510s 42777.158us 1 1 100.00
hmac_test_hmac256_vectors 6.700s 402.306us 1 1 100.00
hmac_test_hmac384_vectors 7.630s 501.046us 1 1 100.00
hmac_test_hmac512_vectors 7.790s 1669.851us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 8.260s 854.802us 1 1 100.00
hmac_long_msg 44.560s 12729.175us 1 1 100.00
hmac_back_pressure 37.890s 856.059us 1 1 100.00
hmac_datapath_stress 521.200s 18588.900us 1 1 100.00
hmac_burst_wr 4.470s 300.866us 1 1 100.00
hmac_error 83.350s 76252.706us 1 1 100.00
hmac_wipe_secret 91.780s 21117.616us 1 1 100.00
hmac_test_sha256_vectors 181.270s 5219.129us 1 1 100.00
hmac_test_sha384_vectors 21.220s 239.453us 1 1 100.00
hmac_test_sha512_vectors 354.510s 42777.158us 1 1 100.00
hmac_test_hmac256_vectors 6.700s 402.306us 1 1 100.00
hmac_test_hmac384_vectors 7.630s 501.046us 1 1 100.00
hmac_test_hmac512_vectors 7.790s 1669.851us 1 1 100.00
hmac_stress_all 1418.620s 84853.548us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 1418.620s 84853.548us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.640s 108.649us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.680s 138.962us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 1.760s 109.477us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 1.760s 109.477us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.730s 19.033us 1 1 100.00
hmac_csr_rw 0.700s 19.645us 1 1 100.00
hmac_csr_aliasing 6.000s 319.293us 1 1 100.00
hmac_same_csr_outstanding 1.030s 457.301us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.730s 19.033us 1 1 100.00
hmac_csr_rw 0.700s 19.645us 1 1 100.00
hmac_csr_aliasing 6.000s 319.293us 1 1 100.00
hmac_same_csr_outstanding 1.030s 457.301us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.850s 39.701us 1 1 100.00
hmac_tl_intg_err 1.430s 392.233us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 1.430s 392.233us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 8.260s 854.802us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 2.220s 370.189us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 80.710s 96632.515us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 0.780s 8.639us 1 1 100.00