Simulation Results

Simulation Results: i2c

21/04/2026 00:01:59 DVSim: v1.32.0 sha: 089baca json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
86.06 %

code
81.53 %

assert
96.41 %

func
80.23 %

line
96.41 %

branch
92.41 %

cond
85.34 %

toggle
89.45 %

FSM
44.05 %

Validation stages

V1		100.00%
V2		87.80%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	40.800s	5339.783us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	8.640s	4472.341us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.820s	29.277us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.660s	51.537us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	3.680s	369.221us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.160s	125.571us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	0.800s	86.943us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.660s	51.537us	1	1	100.00
	i2c_csr_aliasing	1.160s	125.571us	1	1	100.00

36/41 passed

87.80 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	0.660s	11.207us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	146.520s	6193.942us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	547.290s	26735.566us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.740s	162.737us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	137.580s	16760.307us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	53.030s	6072.616us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	0.870s	482.758us	1	1	100.00
	i2c_host_fifo_fmt_empty	3.820s	1651.326us	1	1	100.00
	i2c_host_fifo_reset_rx	2.230s	239.620us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	38.350s	4973.763us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	11.060s	1688.321us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	0.750s	56.915us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	2.120s	532.188us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	29.240s	63353.443us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	3.770s	2829.066us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	14.640s	1946.023us	1	1	100.00
	i2c_target_intr_smoke	5.830s	3256.910us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	1.550s	366.101us	1	1	100.00
	i2c_target_fifo_reset_tx	1.460s	221.005us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	469.410s	45779.919us	1	1	100.00
	i2c_target_stress_rd	14.640s	1946.023us	1	1	100.00
	i2c_target_intr_stress_wr	22.790s	13703.232us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	4.250s	4261.903us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	16.530s	5377.290us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	3.600s	5798.459us	1	1	100.00
target_mode_glitch				0	1	0.00
	i2c_target_hrst	5.090s	11177.411us	0	1	0.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	2.850s	2286.442us	1	1	100.00
	i2c_target_fifo_watermarks_tx	1.400s	130.792us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	547.290s	26735.566us	1	1	100.00
	i2c_host_perf_precise	158.460s	5836.101us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	11.060s	1688.321us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	3.880s	263.787us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	1.710s	397.055us	1	1	100.00
	i2c_target_nack_acqfull_addr	1.960s	618.320us	1	1	100.00
	i2c_target_nack_txstretch	1.730s	177.073us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	5.730s	3948.672us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	1.770s	377.298us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.910s	25.085us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.790s	16.761us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	1.390s	303.675us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	1.390s	303.675us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.820s	29.277us	1	1	100.00
	i2c_csr_rw	0.660s	51.537us	1	1	100.00
	i2c_csr_aliasing	1.160s	125.571us	1	1	100.00
	i2c_same_csr_outstanding	0.960s	41.496us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.820s	29.277us	1	1	100.00
	i2c_csr_rw	0.660s	51.537us	1	1	100.00
	i2c_csr_aliasing	1.160s	125.571us	1	1	100.00
	i2c_same_csr_outstanding	0.960s	41.496us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	1.290s	680.537us	1	1	100.00
	i2c_sec_cm	1.210s	91.569us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.290s	680.537us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	15.580s	1082.077us	1
target_error_intr				1
	i2c_target_unexp_stop	1.630s	215.620us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	10.700s	4240.388us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between
	i2c_host_error_intr	104845548864345486419238820065902801916403094859997496852258390348500711243269	80	UVM_INFO @ 11207198 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_stress_all	25766835975051741001616894683707889349489498226914087174384021413911633600221	100	UVM_INFO @ 6193941549 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between
	i2c_target_glitch	35754567476695884176233581298797329110495950668512847888162228522236664954388	84	UVM_INFO @ 532187577 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:682) [scoreboard] Check failed obs.data_q[i] == exp.data_q[i] (* [] vs [*])
	i2c_target_unexp_stop	100168421093975622086776859217990343289184811794109155320871218849970503103120	78	UVM_INFO @ 215619852 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (i2c_target_hrst_vseq.sv:107) [target_hrst_vseq] wait timeout occurred!
	i2c_target_hrst	82172201359488250334866236735146140422685440576519921087716988465770772576871	79	UVM_INFO @ 11177410720 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1236) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
	i2c_host_stress_all_with_rand_reset	58471610308404779923022500578725091027483935100005015916305810315910707756401	89	UVM_INFO @ 1082076618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_target_stress_all_with_rand_reset	39611126845421722004514656327898842838107728227005630128415132927501764034722	104	UVM_INFO @ 4240388345 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout i2c_reg_block.status.hostidle (addr=, Comparison=CompareOpEq, exp_data=, call_count=3)
	i2c_host_mode_toggle	25048921638778618291762734519650236166904196405465309512732909158043245354157	79	UVM_INFO @ 56914670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---