Simulation Results: keymgr

 
21/04/2026 00:01:59 DVSim: v1.32.0 sha: 089baca json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.56 %
  • code
  • 95.68 %
  • assert
  • 97.72 %
  • func
  • 63.29 %
  • line
  • 98.84 %
  • branch
  • 97.81 %
  • cond
  • 93.88 %
  • toggle
  • 97.17 %
  • FSM
  • 90.70 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_smoke 1.870s 130.375us 1 1 100.00
random 1 1 100.00
keymgr_random 3.360s 351.578us 1 1 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 1.310s 27.142us 1 1 100.00
csr_rw 1 1 100.00
keymgr_csr_rw 1.010s 58.624us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 7.600s 265.593us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 6.020s 135.780us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_csr_mem_rw_with_rand_reset 1.490s 65.913us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_csr_rw 1.010s 58.624us 1 1 100.00
keymgr_csr_aliasing 6.020s 135.780us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 1 1 100.00
keymgr_cfg_regwen 3.370s 76.418us 1 1 100.00
sideload 4 4 100.00
keymgr_sideload 2.230s 238.931us 1 1 100.00
keymgr_sideload_kmac 5.830s 400.611us 1 1 100.00
keymgr_sideload_aes 2.130s 111.746us 1 1 100.00
keymgr_sideload_otbn 3.510s 247.219us 1 1 100.00
direct_to_disabled_state 1 1 100.00
keymgr_direct_to_disabled 3.450s 1518.704us 1 1 100.00
lc_disable 1 1 100.00
keymgr_lc_disable 2.930s 156.732us 1 1 100.00
kmac_error_response 1 1 100.00
keymgr_kmac_rsp_err 3.230s 352.731us 1 1 100.00
invalid_sw_input 1 1 100.00
keymgr_sw_invalid_input 2.910s 138.234us 1 1 100.00
invalid_hw_input 1 1 100.00
keymgr_hwsw_invalid_input 2.920s 170.503us 1 1 100.00
sync_async_fault_cross 1 1 100.00
keymgr_sync_async_fault_cross 5.980s 4720.042us 1 1 100.00
stress_all 1 1 100.00
keymgr_stress_all 27.690s 9097.578us 1 1 100.00
intr_test 1 1 100.00
keymgr_intr_test 0.890s 47.151us 1 1 100.00
alert_test 1 1 100.00
keymgr_alert_test 0.990s 44.632us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_tl_errors 2.670s 48.785us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_tl_errors 2.670s 48.785us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_csr_hw_reset 1.310s 27.142us 1 1 100.00
keymgr_csr_rw 1.010s 58.624us 1 1 100.00
keymgr_csr_aliasing 6.020s 135.780us 1 1 100.00
keymgr_same_csr_outstanding 2.740s 452.581us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_csr_hw_reset 1.310s 27.142us 1 1 100.00
keymgr_csr_rw 1.010s 58.624us 1 1 100.00
keymgr_csr_aliasing 6.020s 135.780us 1 1 100.00
keymgr_same_csr_outstanding 2.740s 452.581us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
keymgr_sec_cm 8.330s 1973.554us 1 1 100.00
tl_intg_err 2 2 100.00
keymgr_sec_cm 8.330s 1973.554us 1 1 100.00
keymgr_tl_intg_err 7.940s 328.158us 1 1 100.00
shadow_reg_update_error 1 1 100.00
keymgr_shadow_reg_errors 1.380s 215.534us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
keymgr_shadow_reg_errors 1.380s 215.534us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
keymgr_shadow_reg_errors 1.380s 215.534us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
keymgr_shadow_reg_errors 1.380s 215.534us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
keymgr_shadow_reg_errors_with_csr_rw 3.290s 106.826us 1 1 100.00
prim_count_check 1 1 100.00
keymgr_sec_cm 8.330s 1973.554us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_sec_cm 8.330s 1973.554us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
keymgr_tl_intg_err 7.940s 328.158us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
keymgr_shadow_reg_errors 1.380s 215.534us 1 1 100.00
sec_cm_op_config_regwen 1 1 100.00
keymgr_cfg_regwen 3.370s 76.418us 1 1 100.00
sec_cm_reseed_config_regwen 2 2 100.00
keymgr_random 3.360s 351.578us 1 1 100.00
keymgr_csr_rw 1.010s 58.624us 1 1 100.00
sec_cm_sw_binding_config_regwen 2 2 100.00
keymgr_random 3.360s 351.578us 1 1 100.00
keymgr_csr_rw 1.010s 58.624us 1 1 100.00
sec_cm_max_key_ver_config_regwen 2 2 100.00
keymgr_random 3.360s 351.578us 1 1 100.00
keymgr_csr_rw 1.010s 58.624us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
keymgr_lc_disable 2.930s 156.732us 1 1 100.00
sec_cm_constants_consistency 1 1 100.00
keymgr_hwsw_invalid_input 2.920s 170.503us 1 1 100.00
sec_cm_intersig_consistency 1 1 100.00
keymgr_hwsw_invalid_input 2.920s 170.503us 1 1 100.00
sec_cm_hw_key_sw_noaccess 1 1 100.00
keymgr_random 3.360s 351.578us 1 1 100.00
sec_cm_output_keys_ctrl_redun 1 1 100.00
keymgr_sideload_protect 1.200s 103.995us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 8.330s 1973.554us 1 1 100.00
sec_cm_data_fsm_sparse 1 1 100.00
keymgr_sec_cm 8.330s 1973.554us 1 1 100.00
sec_cm_ctrl_fsm_local_esc 1 1 100.00
keymgr_sec_cm 8.330s 1973.554us 1 1 100.00
sec_cm_ctrl_fsm_consistency 1 1 100.00
keymgr_custom_cm 1.770s 93.578us 1 1 100.00
sec_cm_ctrl_fsm_global_esc 1 1 100.00
keymgr_lc_disable 2.930s 156.732us 1 1 100.00
sec_cm_ctrl_ctr_redun 1 1 100.00
keymgr_sec_cm 8.330s 1973.554us 1 1 100.00
sec_cm_kmac_if_fsm_sparse 1 1 100.00
keymgr_sec_cm 8.330s 1973.554us 1 1 100.00
sec_cm_kmac_if_ctr_redun 1 1 100.00
keymgr_sec_cm 8.330s 1973.554us 1 1 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 1 1 100.00
keymgr_custom_cm 1.770s 93.578us 1 1 100.00
sec_cm_kmac_if_done_ctrl_consistency 1 1 100.00
keymgr_custom_cm 1.770s 93.578us 1 1 100.00
sec_cm_reseed_ctr_redun 1 1 100.00
keymgr_sec_cm 8.330s 1973.554us 1 1 100.00
sec_cm_side_load_sel_ctrl_consistency 1 1 100.00
keymgr_custom_cm 1.770s 93.578us 1 1 100.00
sec_cm_sideload_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 8.330s 1973.554us 1 1 100.00
sec_cm_ctrl_key_integrity 1 1 100.00
keymgr_custom_cm 1.770s 93.578us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
keymgr_stress_all_with_rand_reset 6.160s 340.718us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
keymgr_stress_all_with_rand_reset 41731969576615866146160222350660157335456487819622367722690481945152202853181 985
UVM_INFO @ 340718153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---