Simulation Results: kmac/masked

 
21/04/2026 00:01:59 DVSim: v1.32.0 sha: 089baca json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 93.85 %
  • code
  • 90.16 %
  • assert
  • 97.98 %
  • func
  • 93.41 %
  • line
  • 98.80 %
  • branch
  • 96.04 %
  • cond
  • 91.59 %
  • toggle
  • 99.59 %
  • FSM
  • 64.79 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 30.500s 1994.645us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 1.110s 56.614us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 1.260s 144.914us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 15.300s 1529.028us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 3.800s 813.715us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 1.620s 49.953us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 1.260s 144.914us 1 1 100.00
kmac_csr_aliasing 3.800s 813.715us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.880s 22.560us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.260s 21.274us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 317.230s 16447.060us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 431.570s 31421.375us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 1796.150s 70233.578us 1 1 100.00
kmac_test_vectors_sha3_256 25.850s 1293.754us 1 1 100.00
kmac_test_vectors_sha3_384 1241.090s 89047.241us 1 1 100.00
kmac_test_vectors_sha3_512 1062.650s 258368.115us 1 1 100.00
kmac_test_vectors_shake_128 1811.590s 86378.484us 1 1 100.00
kmac_test_vectors_shake_256 1868.120s 169706.031us 1 1 100.00
kmac_test_vectors_kmac 2.350s 322.765us 1 1 100.00
kmac_test_vectors_kmac_xof 2.160s 106.300us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 358.740s 22794.470us 1 1 100.00
app 1 1 100.00
kmac_app 165.900s 14200.331us 1 1 100.00
app_with_partial_data 1 1 100.00
kmac_app_with_partial_data 77.450s 16020.137us 1 1 100.00
entropy_refresh 1 1 100.00
kmac_entropy_refresh 214.630s 52946.055us 1 1 100.00
error 1 1 100.00
kmac_error 46.550s 2102.440us 1 1 100.00
key_error 1 1 100.00
kmac_key_error 4.070s 595.595us 1 1 100.00
sideload_invalid 1 1 100.00
kmac_sideload_invalid 2.480s 438.105us 1 1 100.00
edn_timeout_error 1 1 100.00
kmac_edn_timeout_error 32.620s 1901.783us 1 1 100.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 0.750s 68.877us 1 1 100.00
entropy_ready_error 1 1 100.00
kmac_entropy_ready_error 5.460s 2441.590us 1 1 100.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.230s 27.974us 1 1 100.00
stress_all 1 1 100.00
kmac_stress_all 1128.830s 47520.177us 1 1 100.00
intr_test 1 1 100.00
kmac_intr_test 0.940s 51.985us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 0.780s 48.744us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 1.600s 230.782us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 1.600s 230.782us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 1.110s 56.614us 1 1 100.00
kmac_csr_rw 1.260s 144.914us 1 1 100.00
kmac_csr_aliasing 3.800s 813.715us 1 1 100.00
kmac_same_csr_outstanding 1.510s 255.894us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 1.110s 56.614us 1 1 100.00
kmac_csr_rw 1.260s 144.914us 1 1 100.00
kmac_csr_aliasing 3.800s 813.715us 1 1 100.00
kmac_same_csr_outstanding 1.510s 255.894us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.250s 36.645us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.250s 36.645us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.250s 36.645us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.250s 36.645us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 4.430s 1543.118us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_sec_cm 77.800s 27727.016us 1 1 100.00
kmac_tl_intg_err 3.780s 190.008us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 3.780s 190.008us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.230s 27.974us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 30.500s 1994.645us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 358.740s 22794.470us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.250s 36.645us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 77.800s 27727.016us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 77.800s 27727.016us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 77.800s 27727.016us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 30.500s 1994.645us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.230s 27.974us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 77.800s 27727.016us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 1 1 100.00
kmac_mubi 216.200s 76090.306us 1 1 100.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 30.500s 1994.645us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
kmac_stress_all_with_rand_reset 37.690s 4433.031us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1236) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
kmac_stress_all_with_rand_reset 107643326931376184105175294710337037431706417604815291873692961464242565226361 249
UVM_INFO @ 4433031051 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---