Simulation Results: lc_ctrl/volatile_unlock_disabled

 
21/04/2026 00:01:59 DVSim: v1.32.0 sha: 089baca json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.07 %
  • code
  • 85.02 %
  • assert
  • 93.72 %
  • func
  • 94.48 %
  • line
  • 97.17 %
  • branch
  • 93.82 %
  • cond
  • 79.17 %
  • toggle
  • 88.58 %
  • FSM
  • 66.36 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.750s 71.470us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.980s 23.938us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.880s 14.761us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.100s 266.013us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 0.860s 26.029us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.270s 25.339us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.880s 14.761us 1 1 100.00
lc_ctrl_csr_aliasing 0.860s 26.029us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 2.180s 90.414us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 15.180s 3343.379us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.100s 16.095us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.240s 102.495us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 9.390s 1660.372us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 4.760s 1158.915us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 9.390s 1660.372us 1 1 100.00
lc_ctrl_prog_failure 2.240s 102.495us 1 1 100.00
lc_ctrl_errors 4.760s 1158.915us 1 1 100.00
lc_ctrl_security_escalation 6.970s 8587.689us 1 1 100.00
lc_ctrl_jtag_state_failure 16.640s 1611.620us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.240s 920.106us 1 1 100.00
lc_ctrl_jtag_errors 24.120s 3029.845us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 5.980s 293.391us 1 1 100.00
lc_ctrl_jtag_state_post_trans 11.670s 1614.869us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.240s 920.106us 1 1 100.00
lc_ctrl_jtag_errors 24.120s 3029.845us 1 1 100.00
lc_ctrl_jtag_access 2.370s 77.098us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 9.900s 814.843us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.060s 377.160us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.810s 217.944us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 13.350s 1602.872us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 15.370s 3090.360us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.550s 75.547us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 2.260s 130.995us 1 1 100.00
lc_ctrl_jtag_alert_test 2.950s 160.023us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 6.070s 2400.236us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.090s 22.515us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 64.760s 29649.025us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.050s 21.858us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.760s 26.517us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.760s 26.517us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.980s 23.938us 1 1 100.00
lc_ctrl_csr_rw 0.880s 14.761us 1 1 100.00
lc_ctrl_csr_aliasing 0.860s 26.029us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.890s 23.856us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.980s 23.938us 1 1 100.00
lc_ctrl_csr_rw 0.880s 14.761us 1 1 100.00
lc_ctrl_csr_aliasing 0.860s 26.029us 1 1 100.00
lc_ctrl_same_csr_outstanding 0.890s 23.856us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 9.050s 433.686us 1 1 100.00
lc_ctrl_tl_intg_err 1.500s 184.404us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.500s 184.404us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 15.180s 3343.379us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 9.390s 1660.372us 1 1 100.00
lc_ctrl_sec_cm 9.050s 433.686us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 9.390s 1660.372us 1 1 100.00
lc_ctrl_sec_cm 9.050s 433.686us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 9.390s 1660.372us 1 1 100.00
lc_ctrl_sec_cm 9.050s 433.686us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 9.390s 1660.372us 1 1 100.00
lc_ctrl_sec_cm 9.050s 433.686us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 9.390s 1660.372us 1 1 100.00
lc_ctrl_sec_cm 9.050s 433.686us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 9.390s 1660.372us 1 1 100.00
lc_ctrl_sec_cm 9.050s 433.686us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 9.390s 1660.372us 1 1 100.00
lc_ctrl_sec_cm 9.050s 433.686us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 9.390s 1660.372us 1 1 100.00
lc_ctrl_sec_cm 9.050s 433.686us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.970s 8587.689us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 2.180s 90.414us 1 1 100.00
lc_ctrl_jtag_state_post_trans 11.670s 1614.869us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.830s 1230.557us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.830s 1230.557us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 7.940s 1190.332us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.750s 1703.928us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.750s 1703.928us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 45.000s 2169.625us 1 1 100.00