Simulation Results: lc_ctrl/volatile_unlock_enabled

 
21/04/2026 00:01:59 DVSim: v1.32.0 sha: 089baca json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.58 %
  • code
  • 83.85 %
  • assert
  • 94.13 %
  • func
  • 93.77 %
  • line
  • 97.10 %
  • branch
  • 93.47 %
  • cond
  • 79.42 %
  • toggle
  • 83.86 %
  • FSM
  • 65.42 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.150s 165.224us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.270s 81.683us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.800s 52.732us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.770s 69.227us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.130s 47.516us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.050s 58.380us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.800s 52.732us 1 1 100.00
lc_ctrl_csr_aliasing 1.130s 47.516us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 5.780s 98.877us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 6.230s 249.739us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.850s 24.924us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.110s 70.218us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 6.890s 819.461us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 6.910s 513.714us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 6.890s 819.461us 1 1 100.00
lc_ctrl_prog_failure 2.110s 70.218us 1 1 100.00
lc_ctrl_errors 6.910s 513.714us 1 1 100.00
lc_ctrl_security_escalation 7.560s 689.727us 1 1 100.00
lc_ctrl_jtag_state_failure 25.570s 16060.555us 1 1 100.00
lc_ctrl_jtag_prog_failure 7.410s 8188.004us 1 1 100.00
lc_ctrl_jtag_errors 30.350s 6075.502us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 4.490s 629.708us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.100s 2613.831us 1 1 100.00
lc_ctrl_jtag_prog_failure 7.410s 8188.004us 1 1 100.00
lc_ctrl_jtag_errors 30.350s 6075.502us 1 1 100.00
lc_ctrl_jtag_access 4.950s 589.169us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 14.040s 5098.377us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.330s 211.123us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.310s 442.154us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 6.590s 342.412us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 8.750s 2187.738us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 0.930s 136.471us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.870s 61.486us 1 1 100.00
lc_ctrl_jtag_alert_test 1.070s 96.757us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 2.000s 606.454us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.830s 25.396us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 13.470s 3721.337us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.890s 72.424us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 4.300s 503.857us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 4.300s 503.857us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.270s 81.683us 1 1 100.00
lc_ctrl_csr_rw 0.800s 52.732us 1 1 100.00
lc_ctrl_csr_aliasing 1.130s 47.516us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.050s 78.223us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.270s 81.683us 1 1 100.00
lc_ctrl_csr_rw 0.800s 52.732us 1 1 100.00
lc_ctrl_csr_aliasing 1.130s 47.516us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.050s 78.223us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.000s 687.543us 1 1 100.00
lc_ctrl_tl_intg_err 1.870s 136.976us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.870s 136.976us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 6.230s 249.739us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 6.890s 819.461us 1 1 100.00
lc_ctrl_sec_cm 6.000s 687.543us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 6.890s 819.461us 1 1 100.00
lc_ctrl_sec_cm 6.000s 687.543us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.890s 819.461us 1 1 100.00
lc_ctrl_sec_cm 6.000s 687.543us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 6.890s 819.461us 1 1 100.00
lc_ctrl_sec_cm 6.000s 687.543us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 6.890s 819.461us 1 1 100.00
lc_ctrl_sec_cm 6.000s 687.543us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.890s 819.461us 1 1 100.00
lc_ctrl_sec_cm 6.000s 687.543us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 6.890s 819.461us 1 1 100.00
lc_ctrl_sec_cm 6.000s 687.543us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 6.890s 819.461us 1 1 100.00
lc_ctrl_sec_cm 6.000s 687.543us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 7.560s 689.727us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 5.780s 98.877us 1 1 100.00
lc_ctrl_jtag_state_post_trans 6.100s 2613.831us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.380s 289.852us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 6.380s 289.852us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 6.410s 291.157us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.510s 1431.684us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.510s 1431.684us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 53.260s 2630.301us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1149) [lc_ctrl_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
lc_ctrl_stress_all_with_rand_reset 85255798728161137484585128222507979800854779288787786813328870319498515733119 15210
UVM_INFO @ 2630300969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---