Simulation Results: otp_ctrl

 
21/04/2026 00:01:59 DVSim: v1.32.0 sha: 089baca json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.66 %
  • code
  • 78.67 %
  • assert
  • 93.92 %
  • func
  • 72.40 %
  • line
  • 88.68 %
  • branch
  • 83.36 %
  • cond
  • 90.24 %
  • toggle
  • 86.26 %
  • FSM
  • 44.79 %
Validation stages
V1
100.00%
V2
85.00%
V2S
77.78%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.470s 70.526us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 4.650s 225.357us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 1.870s 233.257us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.650s 137.772us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 5.450s 503.323us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 4.710s 204.519us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 2.980s 393.425us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.650s 137.772us 1 1 100.00
otp_ctrl_csr_aliasing 4.710s 204.519us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.410s 549.426us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.350s 74.647us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 19.390s 9907.216us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 4.030s 264.330us 1 1 100.00
partition_check 0 2 0.00
otp_ctrl_background_chks 5.170s 318.408us 0 1 0.00
otp_ctrl_check_fail 1.770s 754.991us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 7.830s 4271.264us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 6.220s 506.483us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 20.910s 2397.291us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 12.810s 7693.781us 1 1 100.00
otp_ctrl_parallel_lc_esc 6.260s 187.496us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 76.200s 21379.339us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 1.760s 96.580us 0 1 0.00
test_access 1 1 100.00
otp_ctrl_test_access 16.090s 3684.967us 1 1 100.00
stress_all 1 1 100.00
otp_ctrl_stress_all 49.010s 4103.698us 1 1 100.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.220s 158.519us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.910s 99.066us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 4.320s 141.051us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 4.320s 141.051us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.870s 233.257us 1 1 100.00
otp_ctrl_csr_rw 1.650s 137.772us 1 1 100.00
otp_ctrl_csr_aliasing 4.710s 204.519us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.880s 127.228us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.870s 233.257us 1 1 100.00
otp_ctrl_csr_rw 1.650s 137.772us 1 1 100.00
otp_ctrl_csr_aliasing 4.710s 204.519us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.880s 127.228us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 119.080s 39359.365us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 119.080s 39359.365us 1 1 100.00
otp_ctrl_tl_intg_err 7.620s 1707.065us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 119.080s 39359.365us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 119.080s 39359.365us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 7.620s 1707.065us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 4.650s 225.357us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 4.650s 225.357us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 119.080s 39359.365us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 119.080s 39359.365us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 119.080s 39359.365us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 119.080s 39359.365us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 119.080s 39359.365us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 119.080s 39359.365us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 119.080s 39359.365us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 119.080s 39359.365us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 119.080s 39359.365us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 119.080s 39359.365us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 119.080s 39359.365us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 119.080s 39359.365us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 119.080s 39359.365us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 119.080s 39359.365us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 119.080s 39359.365us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.260s 187.496us 1 1 100.00
otp_ctrl_sec_cm 119.080s 39359.365us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.260s 187.496us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.260s 187.496us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 6.260s 187.496us 1 1 100.00
otp_ctrl_macro_errs 1.760s 96.580us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.260s 187.496us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.260s 187.496us 1 1 100.00
otp_ctrl_sec_cm 119.080s 39359.365us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.260s 187.496us 1 1 100.00
otp_ctrl_sec_cm 119.080s 39359.365us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.260s 187.496us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.260s 187.496us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 6.260s 187.496us 1 1 100.00
otp_ctrl_macro_errs 1.760s 96.580us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 6.260s 187.496us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 6.260s 187.496us 1 1 100.00
otp_ctrl_sec_cm 119.080s 39359.365us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 4.030s 264.330us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 1.770s 754.991us 0 1 0.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 6.220s 506.483us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 6.220s 506.483us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 6.220s 506.483us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 6.220s 506.483us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 6.220s 506.483us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 4.650s 225.357us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 6.220s 506.483us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 4.650s 225.357us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 119.080s 39359.365us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 7.830s 4271.264us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 4.650s 225.357us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 4.650s 225.357us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 1.760s 96.580us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 13.870s 6330.416us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 1.200s 108.459us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1315) [otp_ctrl_background_chks_vseq] Check failed cfg.m_alert_agent_cfgs[alert_name].vif.get_alert() == * (* [*] vs * [*]) fatal error fatal_check_error does not trigger!
otp_ctrl_background_chks 61596356797278417416627916534876175438961746931418056359656289976996969441060 3261
UVM_INFO @ 318407947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_*
otp_ctrl_check_fail 111164814560007933735690055113435469535955551719475808031954465425052240208485 323
UVM_INFO @ 754990580 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:353) scoreboard [scoreboard] alert fatal_macro_error did not trigger max_delay:*
otp_ctrl_macro_errs 70772110531287655276325297881393965099133242862836982003919530584259802714594 233
UVM_INFO @ 96579889 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_scoreboard.sv:632) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = *
otp_ctrl_stress_all_with_rand_reset 103678098260125645384598996031511366771952695343713187957730692633367739892342 95
UVM_INFO @ 108459392 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---